Register Set; Register Address Map; Smcs332Spw Status And Control Registers - Eads Astrium SMCS332SpW User Manual

4 Register Set

This chapter describes the SMCS332SpW registers which can be read or written by the HOCI or via the link (in case the
"control by link" is enabled) to control SMCS332SpW operations. All SMCS332SpW control operations are performed by
writes or reads of the respective registers. Most of the control operations are obvious from the content of the registers.
General Conventions:
- bit 0 (D0) = least significant bit,
- bit 7 (D7) = most significant bit (or bit 15 or bit 31)
- Dx:0 means data bit x until bit 0.
4.1

Register address map

The addresses of the SMCS332SpW registers are directly mapped with pins HADR7 - 0. The tables below shows the
addresses of all the SMCS332SpW registers depending on the HOCI port width.
4.1.1

SMCS332SpW status and control registers

Port Width / Register
Address (hex)
32 16 8
00 00 00 SICR
01 01 01 TRS_CTRL
02 02 02 RT_CTRL
03 03 03
04 04 04 ISR
05
06 06
07
08 08 08 IMR
09
0A 0A
0B
0C 0C 0C COMI_CS0R
0D 0D 0D
0E 0E 0E COMI_ACR
0F 0F 0F PRCIR
SMCS332SpW
User Manual
Function
SMCS332SpW Interface Control Register
Transmit-Speed-Base Register
Routing Enable / Status Register
reserved
Interrupt Status Register
Interrupt Mask Register
COMI Chip Select 0 upper address boundary
Register
reserved
COMI Arbitration Control Register
PRCI Register
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EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue: 1.4
Updated: 9-Sep-2006
Page: 18 of 131
Reset Access
Value
(hex)
00 r / w
0A r / w
00 r / w
00
04010040 ro
00000000 r / w
FF r / w
00
08 r / w
00 r / w