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4.2
Register Description
4.2.1
General SMCS Registers
4.2.1.1
SMCS332SpW Interface Control Register (SICR)
- address:
- data width:
- access mode:
- reset value:
Bit
Description
1:0
00 = Host Control Interface Data Port operates as 8 bit port (RESET)
01 = HOCI data port operates as 16 bit port
1X = HOCI data port operates as 32 bit port
refer also to little/big endian mode of HOCI data port, which is hardware controlled by input level at the
HOSTBIGE pin.
Signal level of HOSTBIGE pin:
2
0 = COMI operates in little endian mode (RESET)
1 = COMI operates in big endian mode
7:3
always '0' / reserved
4.2.1.2
Transmit bitrate base Register (TRS_CTRL)
- address:
- data width:
- access mode:
- reset value:
Bit
Description
4:0
Multiplier value (0x0A after reset), (LSB setting will be ignored)
Value(hex):
0x08
0x0A
0x0C
0x0E
0x10
0x12
0x14
0x00- 0x07 not possible.
7:5
always '0' / reserved
The max. transmit bitrate (in Mbit/s) of all 3 channels is the result of the multiplication between the input frequency at the
CLK10 pin and the multiplier value (MUL). Select the MUL value only to one of the above values. A write of a new value
in the transmit bitrate base register should only be taken when all links are running with 10 MBit/s. After the write of the
new value, the PLL needs 10 us to run on the new frequency. After this time, the links can run with the new transmit bit rate.
SMCS332SpW
User Manual
0x00
3 bit, D2:0
read / write
0x00
0: little endian
1: big endian
0x01
5 bit, D4:0
read / write
0x0A
max. bitrate:
80 Mbit/s
100 Mbit/s
120 Mbit/s (not possible if VCC= 3.3 Volt)
140 Mbit/s (not possible if VCC= 3.3 Volt)
160 Mbit/s (not possible if VCC= 3.3 Volt)
180 Mbit/s (not possible if VCC= 3.3 Volt)
200 Mbit/s (not possible if VCC= 3.3 Volt)
– All Rights Reserved – Copyright per DIN 34 –
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue:
1.4
Updated: 9-Sep-2006
Page:
23 of 131
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