Channel 1 Receive Fifo (Ch1_Rx_Fifo); Channel 1 Status Register (Ch1_Star); Channel 2 Registers; Channel 3 Registers - Eads Astrium SMCS332SpW User Manual

Byte 1 at address 0x2D: (only in 8 bit mode of the HOCI data port):
Bit Description
7:0 upper byte of the current address
4.2.2.23

Channel 1 Receive FIFO (CH1_RX_FIFO)

- address:
- data width:
- access mode:
- reset value:
Beside the communication memory interface the host processor can read data from the receive FIFO interface. The FIFO
data width is equal to the HOCI data port width. The FIFO has a size of 32 bytes. The host processor can control the data
transfer with byte 1/bits 0 and 1 of the interrupt status register (ISR) or with the status bits 2 and 3 of the channel 1 status
register (CH1_STAR). Bit 4 or 5 of the channel 1 status register (CH1_STAR) signals, whether a EOP or EEP character was
received.
4.2.2.24

Channel 1 Status Register (CH1_STAR)

- address:
- data width:
- access mode:
- reset value:
Bit Description
0 transmit FIFO is empty; not changed/reset by read
1 transmit FIFO is full; not changed/reset by read
2 receive FIFO is not empty; not changed/reset by read
3 receive FIFO is full; not changed/reset by read
4 EOP received - reset after read
5 EEP received - reset after read
7:6 always '0' / reserved
4.2.3

Channel 2 Registers

see 4.2.2 Channel 1 Register
4.2.4

Channel 3 Registers

see 4.2.2 Channel 1 Register
SMCS332SpW
User Manual
0x2E
8/16/32 bit, D31:0
read only
0xXXXXXXXX
0x2F
6 bit, D5:0
read only
0x01
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EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue: 1.4
Updated: 9-Sep-2006
Page: 41 of 131