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5.7.2
SMCS332SpW receive time code
Status bits 5, 6 or 7 in register TIME_CNTRL will be set, when the SMCS332SpW receives a time code character over
link1, 2 or 3. If bit 2 of the TIME_CNTRL register is set, the received time code will be written in the TIME_CODE register.
Interrupt generation: See also interrupt bit in ISR Byte 3, bit 6.
TIME_CNTRL
TIME_CNTRL
Bit1
Bit0
0
0
1
1
5.8
SMCS332SpW Version Control
The Software needs often the capability to check which version of the SMCS332 is used, the new SMCS332SpW or the
older SMCS332. The solution for this problem is, the SW can use the new TIME_CNTRL register.
In the old version of the SMCS332 there is no register on this address, therefore when the software writes the value 0x01 to
this address, they will read the value 0x00 from the old SMCS332 and 0x01 from the new SMCS332SpW.
SMCS332SpW
User Manual
Description
0
No interrupt signal to the interrupt controller.
1
Generates an interrupt signal to the interrupt controller for a valid
(TIME_CODE register (bit5-0) + 1) received TIME CODE character received
from the SpaceWire links.
0
Generates an interrupt signal to the interrupt controller for all received TIME
CODE characters.
1
Generates an interrupt signal to the interrupt controller for a invalid TIME
CODE characters received from the SpaceWire links.
– All Rights Reserved – Copyright per DIN 34 –
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue:
1.4
Updated: 9-Sep-2006
Page:
55 of 131
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