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4.2.2.4
Channel 1 SpaceWire Test Register (CH1_DSM_TSTR)
- address:
- data width:
- access mode:
- reset value:
The test register is writeable only when bit 7 of register CH1_DSM_MODR is set. Once this bit has been set it remains so
even when test mode is exited.
Bit
Description
0
enables internal feedback of transmit link to receive link (data will also be transmitted externally)
1
disable disconnect detection
2
link input mute
3
insert wrong parity
If set, inverts the transmitted parity.
The wrong parity bit is used to invert the parity generation bit and so invoke a parity error at the other end
of the link.
The other end of the link detects an error and stops the transmission (= disconnect).
4
link output mute
5
send EEP character instead of an EOP character
7:6
always '0'/reserved
The input mute bit holds the D and S inputs on the reset value '0'
The output mute bit holds the D and S outputs on the reset value '0'.
4.2.2.5
Channel 1 Address Register (CH1_ADDR)
- address:
- data width:
- access mode:
- reset value:
In protocol mode with enabled check destination bit:
The SpaceWire cell compares the first byte (destination address byte) of the received data packet with the value of
register CH1_ADDR. If it does not match, an error condition occurs (see CH1_ESR1).
In wormhole routing mode:
The SpaceWire cell compares the first byte (destination address byte) of the received data packet with the value of
register CH1_ADDR or with the value of register CHx_RT_ADDR from the other two SpaceWire channels. If it does
not match, an error condition occurs (see CH1_ESR1). For more information see chapter 5.5
Bit
Description
7:0
Address of channel 1
SMCS332SpW
User Manual
0x13
4 bit, D3:0
read / write
0x0
0x14
8 bit, D7:0
read / write
0x00
– All Rights Reserved – Copyright per DIN 34 –
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue:
1.4
Updated: 9-Sep-2006
Page:
31 of 131
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