Appendix B. Fec (Forward Error Correction) Options; Fec Overview; Dvb-S2: Ldpc And Bch - Comtec CDM-840 Installation And Operation Manual

Appendix B. FEC (FORWARD
ERROR CORRECTION) OPTIONS
B.1

FEC Overview

The method of FEC (Forward Error Correction) used by the CDM-840 Remote Router depends on
the direction of signal processing in use:
•
The receive (Rx) side of the CDM-840 operates with error correction based on the DVB-S2
standard for QPSK, 8PSK, 16APSK and 32APSK with concatenated Low Density Parity Code
(LDPC) and Bose-Chaudhuri-Hocquenghem (BCH).
•
The transmit (Tx) side of the CDM-840 uses a family of short-block, very low latency, Low
Density Parity Check (LDPC) codes called VersaFEC
that demand the shortest possible latency. It is a patent pending technology wholly owned
and developed by Comtech EF Data and Comtech AHA Enterprise Products Group (the
VersaFEC name is a trademark registered to Comtech AHA).
B.2

DVB-S2: LDPC and BCH

The DVB-S2 specification defines a generation of performance that boosts throughput by about
30% over DVB-S while using the same amount of bandwidth. The result is coding and
modulation that surpasses the capability of concatenated Viterbi and Reed Solomon coding.
LDPC and BCH is also a concatenated error correction technique; the LDPC coding scheme features
significant, Near-Shannon Bound Performance.
In some cases, LDPC error correction starts flaring toward an error floor as the carrier-to-noise ratio
increases. To compensate, BCH error correction follows LDPC and eliminates the flare for any
practical range of error rates.
LDPC also functions differently than Viterbi decoding by using iterative decoding. In this process,
the data initially corrected by the LDPC decoder is re-encoded and run through the decoder
again to correct additional errors. Through soft decision output from the LDPC decoder and a
high-speed processor operating at a rate much higher than the data rate, the iterative process is
run as many times as possible before corrected data is finally output to make way for a new
block of data entering the decoder.
®
. VersaFEC is ideal for lower data rates
B–1