Siemens SIPROTEC 7SA6 Manual page 419

Overvoltage
Negative Sequence
System U
2
Overvoltage
Zero Sequence
System 3⋅U
0
7SA6 Manual
C53000-G1176-C156-2
U U
L1-E
Ph–E
U
L2-E
U
U
1
L3-E
FNo 10204
>U1>(>) BLK
Figure 6-115 Logic diagram of the overvoltage protection for the positive sequence
voltage system
The device calculates the negative sequence system voltages according to its defining
equation:
⋅ (U ⋅ U
1 2
U = / + a
2 3 L1
j120°
with a = e .
The resulting single–phase AC voltage is fed to the two threshold stages U2> and
U2>> . The logic is designed just like in the positive sequence system (Figure 6-115).
Combined with the associated time delays T U2> and T U2>> these stages form a
two-stage overvoltage protection for the negative sequence system. Here too, the
drop-off to pick-up ratio can be set. The overvoltage protection for the negative se-
quence system can also be blocked via a binary input " >U2>(>) BLK ". The stages of
the negative sequence voltage protection are automatically blocked as soon as an
asymmetrical voltage failure was detected ("Fuse–Failure–Monitor", also see Section
6.21.1.3, margin heading "Fuse Failure Monitor (Non-Symmetrical Voltages)") or
when the trip of the mcb for voltage transformers has been signalled via the binary in-
put " >FAIL:Feeder VT " (internal indication "internal blocking").
The stages of the negative sequence voltage protection are automatically blocked
(with the internal automatic reclosure function) during single-pole automatic reclose
dead time, to avoid pick-up with the false negative sequence values arising during this
state. If the device cooperates with an external automatic reclosure function, or if a sin-
gle-pole tripping can be triggered by a different protection system (working in parallel),
the overvoltage protection for the negative sequence system must be blocked via a
binary input during single-pole tripping.
Figure 6-116 depicts the logic diagram of the zero sequence voltage stage. The fun-
damental frequency is numerically filtered from the measuring voltage so that the har-
monics or transient voltage peaks remain largely harmless.
The triple zero sequence voltage 3 U
3U0>> . Combined with the associated time delays T 3U0> and T 3U0>> these stag-
es form a two-stage overvoltage protection for the zero sequence system. Here too,
the drop-off to pick-up ratio can be set ( 3U0>(>) RESET ).
The overvoltage protection for the zero voltage system can also be blocked via a bi-
nary input " >3U0>(>) BLK ". The stages of the zero sequence voltage protection are
automatically blocked as soon as a asymmetrical voltage failure is detected ("Fuse–
Failure–Monitor", also see Section 6.21.1.3, margin heading "Fuse Failure Monitor
(Non-Symmetrical Voltages)") or if the trip of the mcb for voltage transformers has
3732 U1>
U>
3739 U1>(>) RESET
U>>
3734 U1>>
+ a ⋅ U
)
L2 L3
is fed to the two threshold stages 3U0> and
0
T 0
T U1> 3733
≥1
T U1>> 3735
T 0
Functions
FNo 10280
U1> Pickup
FNo 10282
T U1> TimeOut
FNo 10284
U1>(>) TRIP
FNo 10283
T U1>> TimeOut
FNo 10281
U1>> Pickup
6-229