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R&S OSP
The SRE represents the Enable part of an SCPI register. If a bit is set in the SRE and
the associated bit in the STB changes from 0 to 1, the summary bit 6 (MSS) of the
STB is set.
Bit 6 of the SRE is ignored because it corresponds to the summary bit of the STB.
Related common commands
The STB is read out using the command *STB?.
The SRE can be set using command *SRE and read using *SRE?.
The bits in the STB are defined as follows:
Bit No.
2
3
4
5
6
7
6.4.2.2 ESR and ESE
The Event Status Register (ESR) indicates general instrument states. It is linked to the
Event Status Enable (ESE) register on a bit-by-bit basis.
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Related common commands
The Event Status Register (ESR) can be queried using ESR?.
The Event Status Enable (ESE) register can be set using the command *ESE and
read using *ESE?.
The bits in the ESR are defined as follows:
Operating Manual 1505.3896.12 - 14
Meaning
Error Queue not empty
This bit is set when an entry is made in the error queue.
QUEStionable status summary bit
The bit indicates a questionable instrument status, which can be further pinned down by polling
the QUEStionable register.
MAV bit(message available)
This bit is set if a message is available and can be read from the output buffer.
This bit can be used to automatically transfer data from the instrument to the controller.
ESB bit
Sum bit of the event status register. It is set if one of the bits in the event status register is set and
enabled in the event status enable register.
Setting of this bit implies an error or an event which can be further pinned down by polling the
event status register.
MSS bit (master status summary bit)
This bit is set if one of the other bits of this registers is set together with its mask bit in the service
request enable register SRE.
OPERation status register summary bit
This bit is set if an EVENt bit is set in the OPERation-Status register and the associated ENABle
bit is set to 1.
The ESR indicates the current instrument state.
The ESE represents the
and the associated bit in the ESR changes from 0 to 1, the ESB bit in the Status
Byte is set.
Enable
part of an SCPI register. If a bit is set in the ESE
Remote Control
144
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