Block Diagram Of The Digital Board - Tait TM9100 Service Manual

Figure 3.10

Block diagram of the digital board

Trans-
DIG TX INH
mitter
DIG SYN EN
SYN LOCK
DIG SYN TR SW
DIG SYN FAST
Frequency
DIG SYN LATCH
Synthesizer
SYN DIG FREF
DIG SYN SPI DO
DIG SYN SPI CLK
DIG RX LE
RX DIG LD
Receiver
DIG RX NB EN
DIG RX EN
CDC2 DIG SDTO
DIG CDC2 SDTI
DIG CDC2 CLK
DIG CDC2 LRCK
DIG DAC SPI DO
DIG DAC SPI CLK
DIG DAC LATCH
DIG CDC ARSM
CDC DIG VSFS
CDC DIG VSDO
DIG CDC VSDI
CDC DIG BSOFS
CDC DIG BSDO
DIG CDC ASFS
DIG CDC ASDI
CDC DIG ASDO
CODEC
DIG AUD PA EN1
and
DIG AUD PA EN2
Audio
DIG SYS CLK
DIG CDC RST
+1V8
Signal Types:
RF
analog
clock
digital
asynchronous serial data
synchronous serial data
TM9100 Service Manual
© Tait Electronics Limited August 2005
+3V3 +1V8
Digital Board
FPGA
+3V3
RESET
IO
McBSP0
4
McBSP1
4
BIRDIE
System
Clock
FPGA CLOCK
+1V5
FPGA JTAG Signals:
JTAG FPGA TCK
JTAG FPGA TMS
FPGA JTAG TDO
JTAG FPGA TDI
Factory Connector
DGND
Serial AGND
Flash
DIG CH SPI CLK
DIG CH SPI DO
ITF CH SPI DI
DIG CH LE
ITF CH GPI1
DIG CH GPO1
ITF CH PTT
ITF CH HOOK
ITF ON OFF
ITF IOP GPIO1-7
DIG IOP TXD
ITF IOP RXD
ITF AUX GPI1-7
DIG AUX GPO4-7
DIG AUX TXD
ITF AUX RXD
DIG CH TXD
ITF CH RXD
DIG PSU LATCH
DIG WD KICK
DIG TX EN
DIG SLP EN
SRAM
Flash PSU SYS RST
Memory
+1V8
DSP
+1V5 1V5
Regulator
+3V3
+1V8 1V8
Regulator
PSU SYS RST
DIG RX EN
DSP JTAG Signals:
JTAG DSP TCK JTAG
JTAG DSP TMS DSP JTAG EMU0
DSP JTAG TDO DSP JTAG EMU1
JTAG DSP TDI
+3V3
AGND
Circuit Descriptions
Interface
Power
Supply
DSP TRST
89