Generating Pci Cycles - Motorola MVME5100 Programmer's Reference Manual

The PCI Master always removes its request when it receives a disconnect
or a retry.
There is a case where the PCI Master could assert a request but not actually
perform a bus cycle. This may happen if the PCI Master is placed in the
speculative request mode. Refer to the section titled PCI/PPC Contention
Handling for more information. In no case will the PCI Master assert its
request for more than 16 clocks without starting a transaction.
Fast Back-to-Back Transactions
The PCI Master does not generate fast back-to-back transactions.
Arbitration Latency
Because a bulk of the transactions are limited to single-beat transfers on
PCI, the PCI Master does not implement a Master Latency Timer.
Exclusive Access
The PCI Master is not able to initiate exclusive access transactions.
Address/Data Stepping
The PCI Master does not participate in the Address/Data Stepping
protocol.
Parity
The PCI Master supports address parity generation, data parity generation,
and data parity error detection.
Cache Support
The PCI Master does not participate in the PCI caching protocol.

Generating PCI Cycles

There are four basic types of bus cycles that can be generated on the PCI
bus:
http://www.motorola.com/computer/literature
Memory and I/O
Configuration
Special Cycle
Interrupt Acknowledge
Functional Description
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