Mpic Registers; Feature Reporting Register 0; Global Configuration Register 0 - Motorola MVME5100 Programmer's Reference Manual

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller

MPIC Registers

2
MPIC Registers
3 3 2 2 2
1 0 9 8 7
2-108
The following conventions are used in the Hawk register charts:
R - Read Only field.
R/W - Read/Write field.
S - Writing a ONE to this field sets this field.
C - Writing a ONE to this field clears this field.
The MPIC register map is shown in
offset from the base address of the MPIC registers in the PPC-IO or PPC-
Memory space. Note that this map does not depict linear addressing. The
PCI-SLAVE of the PHB has two decoders for generating the MPIC select.
These decoders will generate a select and acknowledge all accesses which
are in a reserved 256K byte range. If the index into that 256K block does
not decode a valid MPIC register address, the logic will return $00000000.
The registers are 8, 16, or 32 bits accessible.
Table 2-19. MPIC Register Map
2 2 2 2 2 2 2 1 1
6 5 4 3 2 1 0 9 8

FEATURE REPORTING REGISTER 0

GLOBAL CONFIGURATION REGISTER 0

MPIC VENDOR IDENTIFICATION REGISTER
PROCESSOR INIT REGISTER
IPI0 VECTOR-PRIORITY REGISTER
IPI1 VECTOR-PRIORITY REGISTER
IPI2 VECTOR-PRIORITY REGISTER
IPI3 VECTOR-PRIORITY REGISTER
Table 2-19. The Off field is the address
1 1 1 1 1 1 1 1
7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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Off
$01000
$01020
$01080
$01090
$010a0
$010b0
$010c0
$010d0
SP REGISTER $010e0