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Servicing the Agilent 16522A
Address Counter Test
Address Counter Test
The Address Counter Test contains four subtests that check the functionality
of the column and row address counters for module RAM. The four subtests
use each of the four loop registers to perform the test.
The first step of the test is to load memory using the current loop register
with a specific pattern for the address counter. Memory is loaded with
0x0000 except at predetermined RAM row and column positions, which are
loaded with 0xFFFF.
The current loop register is used to set the address for the 0xFFFF loading.
The loop register is also used to reset the addresses back to zero for starting
the stepping process.
After memory has been loaded the clock is stepped through all possible RAM
addresses checking for the correct data at each address.
Passing the Address Counter Test implies that each RAM memory location
can be accessed by the RAM addressing circuitry while under control of the
clocking circuit. Passing the test also implies that the loop registers are
operating correctly.
DIAGNOSTIC INTEGER VALUE:
This test checks the counters of the entire module so the diagnostic integer
will be valid for the master card and all expander-configured cards. The
returned integer for a particular card has the following format:
BIT #:
15
14, 13, 12, 11, 10, 9, 8, 7, 6
Row/Col
Fail row
Bit 15 is used to flag where the value of the fail row bits (6-14) came from. If
the failing row value was less than 511 bit 15 is set to zero. If the failing row
was greater than 511 bit 15 is set to one. The failed row bits (6-14) contain a
value from 0 to 255.
Bits 0-5 contain the failure code for the six RAMs on the board. Bits 0-4
contain the failure code for the RAM for pods 1-5, and bit 5 contains the
failure code for the RAM used for instructions. A one in the bit position
indicates that that ram provided incorrect information.
4–16
5, 4, 3, 2, 1, 0
Failed RAM
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