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Servicing the Agilent 16522A
Theory of Operation
Output Driver
The output driver circuit is made up of a series of latch/logic translators and
multiplexers. The latch/translators convert the working-level TTL signals to
output-level ECL signals for each channel. The ECL-level signals are then
directed to the multiplexers.
The multiplexers, one per channel, direct the programmed data patterns to
the output channels. The single-ended ECL-level signals are converted to
differential signals which are routed to the output cables and to the pods.
Note that the differential ECL output signal of the pattern generator module
is not suitable to directly drive ECL circuitry.
Clock Circuit
The clock circuit paces the loop register, the RAM address circuitry, and the
multiplexers in the output driver according to the desired data rate. A 200
MHz clock source is directed through a divider circuit which provides a
100MHz and 50MHz clock in addition to 200MHz. The 200MHz, 100MHz,
50MHz and external clock signals are routed to a clock select multiplexer.
The output of the multiplexer, which represents the user-selected clocking
rate, is distributed to the above listed subcircuits on both the master board
and all expander boards that are configured with the master board.
The output of the clock select multiplexer is also distributed to an external
clock out circuit. The clock signal is routed to a bank of external clock delays,
and then to an external clock delay select multiplexer. The output of this
multiplexer, which represents the desired clock delay, is directed to the
external clock out pin on the clock pod. Consequently, either the internal
clock or external clock is redirected to the clock out pin on the clock pod
with a user-selected clock delay.
CPU Interface
The CPU interface is a single programmable-logic device which interprets the
16500B/C Logic Analysis System backplane logic and translates the logic into
signals to drive and program the pattern generator module.
Pod
The Clock or Data Pod converts the differential output ECL signal to the logic
levels of interest. Because the output of the pattern generator module cannot
directly drive ECL circuitry, the Clock and Data Pod is required to interface
the pattern generator with the target system.
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