High-Level I/O Memory Map For Dsp Subsystem; The Two Parts Of A Dma Controller Transfer; Channels And Port Accesses - Texas Instruments OMAP5910 Reference Manual

Figure 66.

High-Level I/O Memory Map for DSP Subsystem

7.2.3

Channels and Port Accesses

Figure 67.

The Two Parts of a DMA Controller Transfer

SPRU890A
Note:
The I/O memory map varies from device to device due to the different mixes
of peripherals. For a detailed I/O memory map, see the device-specific data
manual.
Word addresses
(Hexadecimal range)
0000-FFFF
The DMA controller has six paths, called channels, to transfer data among the
four standard ports (for DARAM, SARAM, DSP external memory, and
peripherals). Each channel reads data from one port (from the source) and
writes data to that same port or another port (to the destination).
Each channel has a first in, first out (FIFO) buffer that allows the data transfer
to occur in two stages (see Figure 67):
Port read access: Transfer of data from the source port to the channel
-
FIFO buffer.
Port write access: Transfer of data from the channel FIFO buffer to the
-
destination port.
Read access
Source
port
I/O space (Hexadecimal range)
Write access
Channel n
FIFO buffer
n = 0, 1, 2, 3, 4, or 5
DSP Subsystem
DSP DMA
Byte addresses
0 0000-1 FFFF
Destination
port
125