Texas Instruments OMAP5910 Reference Manual page 157

7.2.15.2 Interrupt Multiplexing
7.2.15.3 Timeout Error Conditions
SPRU890A
Each channel interrupt is routed directly to the DSP core via the DSP Level 1
Interrupt Handler. A timeout event generates a bus error interrupt to the DSP
core.
For more information on the DSP subsystem interrupt handlers, see the
OMAP5910 Dual-Core Processor DSP Subsystem Interrupts Reference
Guide (SPRU923) or the OMAP5912 Multimedia Processor Interrupts
Reference Guide (SPRU757).
A timeout error condition exists when a memory access has been stalled for
too many cycles. Three of the four standard ports of the DMA controller are
supported by hardware to detect a timeout error:
DARAM port: A timeout counter in the DARAM port counts how many
-
cycles have passed since a request was made to access the DARAM.
When the counter reaches its timeout value of 255 DSP core clock cycles,
the DARAM port generates an internal timeout signal. This counter can be
enabled or disabled by writing to the DARAM timeout counter enable bit
(DTCE in DMAGTCR). A timeout error on the DARAM port can occur
because the DSP core is using the port and preventing access by the DMA
controller, or because an address was specified that does not exist in the
DARAM of the DSP subsystem.
SARAM port: A timeout counter in the SARAM port counts how many
-
cycles have passed since a request was made to access the SARAM.
When the counter reaches its timeout value of 255 DSP core clock cycles,
the SARAM port generates a timeout signal. This counter can be enabled
or disabled by writing to the SARAM timeout counter enable bit (STCE in
DMAGTCR). A timeout error on the SARAM port can occur because the
DSP core is using the port and preventing access by the DMA controller,
or because an address was specified that does not exist in the SARAM of
the DSP subsystem.
External memory port: The EMIF port does not support a timeout feature.
-
Peripheral port: A timeout counter in the TIPB bridge module counts how
-
many cycles have passed since a request was made to access a
peripheral. When the counter reaches its timeout value of 127 DSP core
clock cycles, the peripheral bus controller sends a timeout signal to the
DMA controller. A timeout error on the peripheral port can occur because
an address was specified that does not exist in I/O space on the DSP.
DSP DMA
DSP Subsystem 157