Texas Instruments OMAP5910 Reference Manual page 220

DSP Subsystem Reset, Clocking, Idle Control, and Boot
Table 96. Idle Domains in the DSP (Continued)
Domain Contents of the Domain
CACHE Instruction cache
EMIF External memory interface (EMIF)
12.3.2.2 Idle Configuration Process
220 DSP Subsystem
The idle configuration indicates which idle domains will be idle and which idle
domains will be active the next time the IDLE instruction is executed. The basic
steps to the idle configuration process are:
1) Define a new idle configuration by writing to the bits in the idle
configuration register (ICR). Make sure that you use a valid idle
configuration (see section 12.3.2.3).
2) Apply the new idle configuration by executing the IDLE instruction. The
effects are shown in Figure 105. The content of ICR is copied to the idle
status register (ISTR). The bits of ISTR are then propagated through the
system to enable or disable each of the chosen domains.
The IDLE instruction cannot be executed in parallel with another instruction.
Note:
If you intend to switch among multiple idle configurations, ensure that your
system has the means to change from one idle configuration to the next. For
important considerations, see section 12.3.2.4.
Configurability
When the IDLE instruction is executed, the instruction
cache remains active or becomes idle, depending on the
chosen idle configuration.
Regardless of this domain's state before a DSP
subsystem reset, it is active after a DSP subsystem reset.
When the IDLE instruction is executed, the EMIF is
disabled or enabled, depending on the chosen idle
configuration.
Regardless of this domain's state before a DSP
subsystem reset, it is active after a DSP subsystem reset.
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