Memory Maps; Omap5910/5912 Dsp Subsystem Global Memory Map - Texas Instruments OMAP5910 Reference Manual

3.4

Memory Maps

Table 1.

OMAP5910/5912 DSP Subsystem Global Memory Map

Byte Address Range
0x00 0000-0x00 FFFF
0x01 0000-0x02 7FFF
0x02 8000-0xFF 7FFF
0xFF 8000-0xFF FFFF
†
This space could be DSP external memory or internal shared system memory, depending on the DSP MMU configuration.
SPRU890A
DSP public peripherals are connected to the DSP public peripheral bus
-
and are directly accessible by the DSP core and DSP DMA. These
peripherals may also be accessed by the MPU core and system DMA
controller via the MPUI.
DSP private peripherals are on the DSP private peripheral bus, and thus,
-
can only be accessed by the DSP core.
To read or write to these registers, you must access the DSP subsystem I/O
space either through C language constructs or, in the case of
assembly-language code, by using a special instruction qualifier called the
memory-mapped register access qualifier. For more details about this
qualifier, see TMS320C55x DSP Mnemonic Instruction Set Reference Guide
(SPRU374).
Note:
Byte access to I/O space is not supported.
The TI peripheral bus bridges manage accesses to the I/O memory space via
two peripheral buses: a private TI peripheral bus and a public TI peripheral
bus. Section 8 describes the TI peripheral bus bridges and their buses.
Table 1 shows the high-level program/data memory map for the DSP
subsystem. DSP core data accesses utilize 16-bit word addresses, while DSP
core program fetches utilize byte addressing. DSP DMA data fetches always
use byte addresses.
Word Address Range
0x00 0000-0x00 7FFF
0x00 8000-0x01 3FFF
0x01 4000-0x7F BFFF
0x7F C000-0x7F FFFF
The I/O memory map varies from device to device, due to the different peripheral
mixes. For a detailed I/O memory map, see the device-specific data manual.
DSP Subsystem Memory
Internal Memory DSP External
Memory
DARAM 64K bytes
SARAM 96K bytes
Managed by DSP
MMU
PDROM Managed by DSP
(MPNMC = 0) MMU (MPNMC = 1)
DSP Subsystem
†
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