Mmu Pre-Fetch Status Register (Walking_St_Reg); Mmu Control Register (Cntl_Reg) - Texas Instruments OMAP5910 Reference Manual

DSP Memory Management Unit
Table 23. MMU Pre-Fetch Status Register (WALKING_ST_REG) Field Descriptions
Bits Field
31−2
Reserved
1
WALK_WORKING
0
PREFETCH_ON
6.5.4

MMU Control Register (CNTL_REG)

Figure 50. MMU Control Register (CNTL_REG)
31
Note: R = Read; W = Write; −n = Value after reset; −x = Value after reset is not defined.
104 DSP Subsystem
Value Description
These bits are not used.
This bit is used to indicate when the table walking logic is performing
an address translation after a miss in the TLB.
0 Table walking logic is not performing any action.
1 Table walking logic is performing an address translation.
This bit is used to indicate the status of a TLB-entry pre-fetch
operation. When a value is written into the PREFETCH_REG register,
the pre-fetch operation is started and this bit is set. When the pre-fetch
operation finishes, this bit is automatically cleared by the MMU.
0 The pre-fetch operation has been completed.
1 A value has been written to the PREFETCH_REG and the table
walking logic is fetching the entry for the TLB.
The Control Register (CNTL_REG) is used to reset and enable the DSP MMU
module and to enable the table walking logic.
Note:
The DSP MMU module must be reset through the MMU_RESET bit of the
CNTL_REG register before the MMU is enabled.
Reserved
R-0
3 2
TWL_EN MMU_EN
RW-0
1 0
MMU_
RESET
RW-0 RW-0
SPRU890A