Texas Instruments OMAP5910 Reference Manual page 43

4.2.10.2 Miss Penalty
SPRU890A
The miss penalty is the time required for the I-Cache to deliver the 32-bit
requested word to the DSP core in the case of a miss (when the word must be
fetched from DSP external memory). In response to a miss, the I-Cache
requests four words from the external memory interface (EMIF) to load the
appropriate line.
The miss penalty due to an initial request to the EMIF is:
1) Four cycles for the I-Cache to receive the fetch request, detect an I-Cache
miss, and forward the fetch request to the EMIF.
2) X cycles for the EMIF to get the requested word to the I-Cache, where X
depends on factors such as:
a) The access latency introduced by the traffic controller.
b) The position of the requested word in the I-Cache line. For example,
if the requested word is the third word of the line, two words are
fetched before the requested word.
c) Whether the four words are fetched in a burst access (if synchronous
memory is used).
3) Three cycles for the I-Cache to get the requested 32-bit word to the
instruction fetch unit (I unit) of the DSP core.
Subsequent requests can incur a smaller miss penalty if the DSP external
memory is synchronous. After accessing the first word from synchronous
memory, the EMIF can return each of the remaining words in a single cycle.
The I-Cache includes a feature that reduces overall miss penalties. The
I-Cache gives the requested word to the DSP core as soon as it arrives in the
I-Cache line, rather than after the whole line is loaded.
Note:
The DSP external memory address generated by the EMIF is a virtual
address. This virtual address is mapped to a physical address within the
memory space of the OMAP device by the DSP Memory Management Unit
(MMU). Before enabling the I-Cache, you must configure the DSP MMU
such that the correct physical address is read during line fill operations.
section 6 describes the DSP MMU).
Instruction Cache
DSP Subsystem 43