Texas Instruments OMAP5910 Reference Manual page 72

DSP Memory Management Unit
72 DSP Subsystem
The preserved parameter of the TLB entry value determines the behavior of
an entry in the event of a TLB flush. If an entry is preserved, it is not deleted
upon a TLB global flush. Section 6.2.2.6 describes the TLB flushing
mechanism.
The size bits determine the range of memory addresses to which the TLB entry
corresponds. All addresses that fall within the same range will have the same
section or base address. For example, external memory addresses between
virtual address 0x10 0000 − 0x1F FFFF will have the same section base
address (0x1).
The physical address tag of the RAM value is a 22-bit field which is used in the
virtual-to-physical address translation, as described in section 6.2.2.2. The
physical address tag is derived from the physical address corresponding to the
virtual address. Note that, like the virtual address tag, not all the bits in the
physical address tag are used. When writing RAM entries to the TLB, unused
bits in the physical address tags must always be kept as zeros. Figure 28
shows how to determine the physical address tag from the physical address.
The access permission bits of the RAM value define the type of access that
is permitted to the physical memory range described by the TLB entry. The
memory range is specified by the physical address tag and the size bits. A
forbidden access to the physical memory will cause the MMU to generate a
permission fault and an interrupt to the MPU core.
SPRU890A