Instruction Cache Blocks; 2-Way Cache - Texas Instruments OMAP5910 Reference Manual

Figure 6.

2-Way Cache

Memory bank 1
Set 0 Line 0
Set 1 Line 1
.
.
.
Set 254 Line 254
Set 255 Line 255
.
.
.
Set 510 Line 510
Set 511 Line 511
4.2.2.2 RAM Set Blocks
SPRU890A
Tag array. Each line has a tag field. When the I-Cache receives a 24-bit
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fetch address from the DSP core, the I-Cache interprets bits 23-13 as a
tag. When a line gets filled, the associated tag is stored in the tag field for
that line.
Across the two memory banks, every two lines with the same number belong
to one set. For example, line 0 of memory bank 1 and line 0 of memory bank
2 belong to set 0. When the I-Cache receives a fetch address, the I-Cache
finds the set number in bits 12-4. If the I-Cache must replace one of the lines
in the set, it uses a least-recently used (LRU) algorithm: The line replaced is
the one that has been unused for the longest time. Each set has an LRU bit
that is toggled to indicate which line should be replaced.
Data LV Tag
.
.
.
.
.
.
As shown in Figure 7, RAM set 1 and RAM set 2 each include the following
parts:
Data array. The data array contains 256 lines (0 through 255).
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Line valid (LV) bit array. Each line has a line valid bit. When a line has been
-
loaded, its line valid bit is set. Whenever the I-Cache is flushed, all 256 line
valid bits are cleared, invalidating all the lines. For more information on
flushing the I-Cache, see section 4.2.4.2.
Memory bank 2
LRU Tag LV
DSP Subsystem
Instruction Cache
Data
Line 0
Line 1
.
.
.
Line 254
Line 255
.
.
.
Line 510
Line 511
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