I-Cache Line Flush Registers (Flr0, Flr1) - Texas Instruments OMAP5910 Reference Manual

Table 6. I-Cache Global Control Register (GCR) Bits Field Descriptions (Continued)
Bits Field
8−5 HLFRAMSET_NUMR
4−3 WAY_NUMR
2 STREAMING
1 RAM_FILL_MODE
0 GLOBAL_ENABLE
4.6.3

I-Cache Line Flush Registers (FLR0, FLR1)

SPRU890A
Value Description
Specifies the number of RAM set blocks to enable when
HLFRAMSET_PRESENCE is set.
0000b Enable only RAM set block 1.
xxx1b Enable both RAM set block1 and 2.
Sets the number of ways active in the N-way cache block.
x0b Set N-way cache as 1-way (direct-mapped).
x1b Set N-way cache as 2-way (set-associative).
The principle of streaming is used in order to reduce the miss penalty:
when a read miss occurs, a line load from external memory is started,
and as soon as the requested word of the line arrives, it is sent to the
DSP core. In this manner, the DSP core can continue its execution
before the entire line is loaded. This bit must always be set.
0 Disabled.
1 Enabled. You must always set this bit.
0 This bit must always be set.
1 Always set this bit to 1.
Setting the CAEN bit of the DSP core ST3_55 register enables the
I-Cache. The N-way cache and the two RAM set blocks contain a local
enable bit in their control registers, NWCR and RCR1/2, respectively.
The GLOBAL_ENABLE bit determines whether the local enable bits
are taken into consideration when CAEN is set.
0 The N-way cache and the RAM set blocks are enabled when CAEN
is set only if their local enable bits are set.
1 The entire cache is enabled when CAEN is set; the local enable bits
are ignored.
The I-Cache line flush registers are used to specify the address to be flushed
from the cache.
Note:
These registers are not used, as line flushing is not supported on OMAP5910
and OMAP5912.
Instruction Cache
DSP Subsystem 51