Texas Instruments OMAP5910 Reference Manual page 14

Tables
Tables
1 OMAP5910/5912 DSP Subsystem Global Memory Map
2 Fetch Address Field Descriptions for the 2-Way Cache Register Field Descriptions
3 Fetch Address Field Descriptions for a RAM Set
4 Instruction Presence Check and I-Cache Response
5 Summary of the I-Cache Registers
6 I-Cache Global Control Register (GCR) Bits Field Descriptions
7 I-Cache Line Flush Register 0 (FLR0) Field Descriptions
8 I-Cache Line Flush Register 1 (FLR1) Field Descriptions
9 I-Cache N-way Control Register (NWCR) Field Descriptions
10 I-Cache RAM Set 1 Control Register (RCR1) and RAM Set 2 Control Register
(RCR2) Field Descriptions
11 I-Cache RAM Set 1 Tag Register (RTR1) Field Descriptions
12 I-Cache RAM Set 2 Tag Register (RTR2) Field Descriptions
13 I-Cache Status Register (ISR) Field Descriptions
14 EMIF Requests and Their Priorities
15 EMIF Requests Associated with Dual and Long Data Accesses
16 Summary of the EMIF Registers
17 EMIF Global Control Register (GCR) Field Descriptions
18 EMIF Global Reset Register (GRR) Field Descriptions
19 First−Level Descriptor Contents
20 First−Level Descriptor Contents
21 Summary of DSP MMU Registers
22 MMU Pre-Fetch Register (PREFETCH_REG) Field Descriptions
23 MMU Pre-Fetch Status Register (WALKING_ST_REG) Field Descriptions
24 Control Register (CNTL_REG) Field Descriptions
25 MMU MSB Fault Address Register (FAULT_AD_H_REG) Field Descriptions
26 MMU LSB Fault Address Register (FAULT_AD_L_REG) Field Descriptions
27 MMU Fault Status Register (FAULT_ST_REG) Field Descriptions
28 MMU Interrupt Acknowledge Register (IT_ACK_REG) Field Descriptions
29 MMU MSB Translation Table Register (TTB_H_REG) Field Descriptions
30 MMU LSB Translation Table Register (TTB_L_REG) Field Descriptions
31 MMU Lock/Protect Entry Register (LOCK_REG) Field Descriptions
32 MMU Read/Write TLB Entry Register (LD_TLB_REG) Field Descriptions
33 MMU MSB CAM Entry Register (CAM_H_REG) Field Descriptions
34 MMU LSB CAM Entry Register (CAM_L_REG) Field Descriptions
35 MMU MSB RAM Entry Register (RAM_H_REG) Field Descriptions
14 DSP Subsystem
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48
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60
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86
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101
103
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105
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107
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111
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113
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