Texas Instruments OMAP5910 Reference Manual page 18

Digital Signal Processor Subsystem Overview
18 DSP Subsystem
DSP subsystem interfaces:
-
External memory interface (EMIF) that connects the DSP core to
J
external and loosely coupled memories
MPUI port that permits access to DSP resources by the MPU and
J
system DMA
TIPB that provides two external bus interfaces for private and public
J
peripherals
DSP subsystem peripherals:
-
Private peripherals are on the DSP private peripheral bus, and can
J
only be accessed by the DSP core. DSP private peripherals include:
H Three 32-bit timers
H Watchdog timer
H Interrupt handlers
Public peripherals are on the DSP public peripheral bus. These
J
peripherals are directly accessible by the DSP core and DSP DMA.
The MPU core can also access these peripherals through the MPUI
port. DSP public peripherals include:
H Two multichannel buffered serial ports (McBSPs)
H Two multichannel serial interfaces (MCSIs)
The DSP core and DMA controller also have access to system
J
peripherals (also referred to as shared peripherals). Shared
peripherals are connected to both the MPU public peripheral bus and
the DSP public peripheral bus. Shared peripherals include:
H Mailbox module to permit interrupt-based signaling between the
DSP and MPU cores
Three universal asynchronous receiver/transmitter (UART)
H
modules
General-purpose input/output (GPIO) module
H
The OMAP5912 also adds these shared peripherals:
J
Eight general purpose timers
H
Serial port interface (SPI)
H
I2C master/slave interface
H
Extra McBSP
H
H Multimedia card/secure digital interface (MMC/SDIO)
32-KHz synchronization counter
H
This document describes all of the DSP module components listed above. The
DSP subsystem peripherals are described in separate documents.
SPRU890A