System Traffic Considerations - Texas Instruments OMAP5910 Reference Manual

DSP Memory Management Unit
6.3.3

System Traffic Considerations

6.4 Using Table Walking Logic to Manage the TLB
6.4.1 Architectural/Operational Description
98 DSP Subsystem
4) Configure the MPU level 2 interrupt handler such that DSP MMU interrupts
are enabled and can be serviced by the MPU core. More information on
the MPU level 2 interrupt handler can be found in the OMAP5912
Multimedia Processor Interrupts Reference Guide (SPRU757).
5) Enable the DSP MMU by setting the MMU_EN bit in CNTL_REG.
6) Take the DSP subsystem out of reset by setting the DSP_EN bit in the
MPU-Reset-Control-1 Register (ARM_RSTCT1).
All DSP subsystem accesses to DSP external memory eventually go through
the traffic controller. The access time for a DSP external memory request will
depend on the amount of competing accesses in the traffic controller, as well
as the configurations of the OMAP external memory interfaces (EMIFF and
EMIFS).
The DSP MMU generates a physical address for every virtual address
generated by the DSP external memory interface (EMIF) by using
address-translation information stored in its TLB. The DSP MMU includes table
walking logic, which automatically fetches the address-translation information
from a set of translation tables and updates the TLB. This section describes the
steps needed to set up the table walking logic to manage the TLB.
Four major steps are taken when the DSP subsystem accesses DSP external
memory.
1) The DSP core or the DSP DMA requests an access to DSP external
memory.
2) The DSP EMIF receives that request and forwards it to the DSP MMU.
SPRU890A