Texas Instruments OMAP5910 Reference Manual page 168

Multimedia processor dsp subsystem
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DSP DMA
Table 63. DMA Channel Control Register (DMACCR) Field Descriptions (Continued)
Bits
Field
9
REPEAT
8
AUTOINIT
7
EN
168
DSP Subsystem
Value
Description
Repeat condition bit. If auto-initialization is selected for a channel
(AUTOINIT = 1), REPEAT specifies one of two special repeat
conditions:
0
Repeat only if ENDPROG = 1. Once the current DMA transfer is
complete, auto-initialization will wait for the end-of-programming bit
(ENDPROG) bit to be set.
1
Repeat regardless of ENDPROG. Once the current DMA transfer is
complete, auto-initialization occurs regardless of whether ENDPROG
is 0 or 1.
Auto-initialization bit. The DMA controller supports auto-initialization,
which is the automatic re-initialization of the channel between DMA
block transfers. Use AUTOINIT to enable or disable this feature.
0
Auto-initialization is disabled. Activity in the channel stops at the end
of the current block transfer. To stop a transfer immediately, clear the
channel enable it (EN).
1
Auto-initialization is enabled. Once the current block transfer is
complete, the DMA controller reinitializes the channel and starts a new
block transfer.
There are two options to stop activity in the channel:
To stop activity immediately, clear the channel enable bit
-
(EN = 0).
To stop activity after the current block transfer, clear AUTOINIT
-
(AUTOINIT= 0).
Channel enable bit. Use EN to enable or disable transfers in the
channel. The DMA controller clears EN when a block transfer in the
channel is complete.
Note: If the DSP core attempts to write to EN at the same time that the
DMA controller must clear EN, the DMA controller is given higher
priority. EN is cleared, and the value from the DSP core is discarded.
0
The channel is disabled. The channel cannot be serviced by the DMA
controller. If a DMA transfer is already active in the channel, the DMA
controller stops the transfer and resets the channel.
1
The channel is enabled. The channel can be serviced by the DMA
controller at the next available time slot.
SPRU890A

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