Dsp Subsystem - Texas Instruments OMAP-L137 User Manual

OMAP-L137
SPRS563G – SEPTEMBER 2008 – REVISED JUNE 2014
3.4

DSP Subsystem

The DSP Subsystem includes the following features:
• C674x DSP CPU
• 32KB L1 Program (L1P)/Cache (up to 32KB)
• 32KB L1 Data (L1D)/Cache (up to 32KB)
• 256KB Unified Mapped RAM/Cache (L2)
• Boot ROM (cannot be used for application code)
• Little endian
32K Bytes
L1P RAM/
Cache
Cache Control
Memory Protect
Bandwidth Mgmt
Instruction Fetch
C674x
Fixed/Floating Point CPU
Register
File A
64
Bandwidth Mgmt
Memory Protect
Cache Control
8 x 32
32K Bytes
L1D RAM/
Cache
12 Device Overview
256
256
L1P
256
256
256
IDMA
Register
File B
64
L1D
Figure 3-1. C674x Megamodule Block Diagram
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Product Folder Links:
256K Bytes Boot ROM
L2 RAM
256
Cache Control
Memory Protect L2
Bandwidth Mgmt
Power Down
256
Interrupt
Controller
256
CFG
EMC
MDMA SDMA
64 64 64 64
High
Performance
Switch Fabric
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256
Configuration
32
Peripherals
Bus