Texas Instruments OMAP5910 Reference Manual page 193

Table 83. TIPB Control Mode Register (CMR) Field Descriptions (Continued)
Bits Field
5−3 ACCESS_
FACTOR0
2 CPU_PRIORITY
1 BUS_ERROR
0 MPUI_MODE
SPRU890A
Value Description
0−7 These bits set the number of wait states inserted when communicating
with peripherals as listed in Table 80 and Table 81.
This bit determines the priority of the DSP core, MPUI, and DSP DMA
controller in the case of simultaneous accesses to the TIPB bridge.
0 Accesses to the TIPB bridge are arbitrated in a rotating priority
fashion: DSP core, MPUI, DSP DMA, DSP core, and so on.
1 Accesses to the TIPB bridge have the following priorities in arbitration:
1) DSP core
2) MPUI
3) DSP DMA
This bit is set when the TIPB generates a bus error to the DSP core
because of a timeout condition or a host-only mode (HOM) change
error or shared-access mode (SAM) change error.
The BUS_ERROR bit is cleared when this register is read by the DSP
core. This bit cannot be read when the MPUI is operating in host-only
mode (register always reads as zero).
0 No bus error has been generated by the TIPB.
1 TIPB has generated a bus error to the DSP core.
This bit indicates whether the MPUI is in host-only mode (HOM) or in
shared-access mode (SAM) for peripherals. Section 9 describes
these modes of the MPUI.
0 MPUI is in shared-access mode.
1 MPUI is in host-only mode.
TI Peripheral Bus Bridges
DSP Subsystem 193