Triggering A Channel Interrupt Request - Texas Instruments OMAP5910 Reference Manual

DSP DMA
7.2.15.1 Channel Interrupt
Figure 80.

Triggering a Channel Interrupt Request

156 DSP Subsystem
Each of the six channels has its own interrupt. As shown in Figure 80, the
channel interrupt is the logical OR of all the enabled operational events except
the timeout event (the timeout event generates a bus-error interrupt request).
You can choose any combination of these five events by setting or clearing the
appropriate interrupt enable (IE) bits in the interrupt control register
(DMACICR) for the channel. You can determine which event(s) caused the
interrupt by reading the bits in the status register (DMACSR) for the channel.
The bits in DMACSR are not automatically cleared. A read of DMACSR clears
all of the status bits. DMACSR should be read each time an interrupt occurs
to clear the pending status bits.
Á Á Á
BLOCKIE
BLOCK event Á Á Á
LASTIE
Á Á Á
LAST event
Á Á Á
FRAMEIE
Á Á Á
FRAME event
Á Á Á
HALFIE
Á Á Á
HALF event
Á Á Á Á Á Á
DROPIE
Á Á Á
DROP event
Á Á Á
As an example of using the interrupt enable bits, suppose you are monitoring
activity in channel 1, and suppose that in DMACICR:
BLOCKIE = 0
LASTIE = 0
FRAMEIE = 1
HALFIE = 0
DROPIE = 1
When the current frame transfer is done or if a synchronization event is
dropped (see section 7.2.12.3), the channel 1 interrupt request is sent to the
DSP core. No other event can generate the channel 1 interrupt. To determine
whether one or both of the events triggered the interrupt, you can read the
FRAME and DROP bits in DMACSR.
The channel 1 interrupt sets its corresponding flag bit in an interrupt flag
register of the DSP core. The DSP core can respond to the interrupt or ignore
the interrupt.
For more details about DMACICR and DMACSR, see section 7.3.6.
Á Á
Á Á Á
Channel interrupt
Á Á Á Á
Á
SPRU890A