(Rcr2) Field Descriptions; I-Cache Ram Set Tag Registers (Rtr1 And Rtr2) - Texas Instruments OMAP5910 Reference Manual

Table 10. I-Cache RAM Set 1 Control Register (RCR1) and RAM Set 2 Control Register

(RCR2) Field Descriptions

Bits Field
15 TAG_VALID
14−2 Reserved
1 FLUSH
0 ENABLE
4.6.6

I-Cache RAM Set Tag Registers (RTR1 and RTR2)

SPRU890A
Value Description
RAM set tag-valid bit. Check this bit to determine when the I-Cache
has completed the process of filling the RAM set.
0 The fill is not started or is not complete.
1 The fill is complete.
These read-only bits are not used.
This bit determines whether the RAM set is flushed when the CACLR
bit of the DSP core ST3_55 register is set. These bit is ignored (RAM
set is always flushed) when GLOBAL_FLUSH is set.
0 The RAM set is not flushed when CACLR is set.
1 The RAM set is flushed when the CACLR is set.
This bit determines whether the RAM set is enabled when the CAEN
bit of the DSP core ST3_55 register is set. This bit is ignored (RAM set
is always enabled) when GLOBAL_ENABLE is set.
0 The RAM set is not enabled when CACLR is set.
1 The RAM set is enabled when the CACLR is set.
For each active RAM set (selected with the global control register), you must
give the I-Cache a 12-bit tag that defines the range of addresses assigned to
that RAM set. Load the tag into the appropriate RAM set tag register. Write a
value with zeros in bits 15-12 and the tag in bits 11-0.
Note:
Do not set the RTR1 and RTR2 registers to the same value.
Instruction Cache
DSP Subsystem 55