Texas Instruments OMAP5910 Reference Manual page 172

DSP DMA
Table 64. DMA Interrupt Control Register (DMACICR) Fields Descriptions (Continued)
Bits Field
3 FRAMEIE
2 HALFIE
1 DROPIE
0 TIMEOUTIE
172 DSP Subsystem
Value Description
Whole frame interrupt enable bit. FRAMEIE determines how the DMA
controller responds when the all of the current frame has been
transferred from the source port to the destination port.
0 Do not record the event.
1 Set the FRAME bit and send the channel interrupt request to the DSP
core.
Half frame interrupt enable bit. HALFIE determines how the DMA
controller responds when the first half of the current frame has been
transferred from the source port to the destination port. For a frame
with an odd number of elements, the half-frame event occurs as soon
as the number of elements transferred is greater than the number that
remains to be transferred. For example, for a frame of five elements,
the half-frame event occurs when the DMA controller has transferred
three of the elements.
0 Do not record the event.
1 Set the HALF bit and send the channel interrupt request to the DSP
core.
Synchronization event drop interrupt enable bit. An error occurs if a
DMA synchronization event occurs again before the DMA controller
has finished servicing the previous DMA request. This error is called
a synchronization event drop. DROPIE determines how the DMA
controller responds when a synchronization event drop occurs in the
channel.
0 Do not record the drop.
1 Set the DROP bit and send the channel interrupt request to the DSP
core.
Timeout interrupt enable bit. TIMEOUTIE determines how the DMA
controller responds to a timeout error at the source port or the
destination port of the channel. Section 7.2.15.3 describes the timeout
error conditions.
0 Do not record the timeout error.
1 Set the TIMEOUT bit and send the bus-error interrupt request to the
DSP core.
SPRU890A