DSP DMA
Table 55. Functional Multiplexing DSP DMA Register B (FUNC_MUX_DSP_DMA_B)
Field Descriptions
Bits
Field
31−30 Reserved
29−25 CONF_DSP_DMA_
EVT_12
24−20 CONF_DSP_DMA_
EVT_11
19−15 CONF_DSP_DMA_
EVT_10
14−10 CONF_DSP_DMA_
EVT_09
9−5
CONF_DSP_DMA_
EVT_08
4−0
CONF_DSP_DMA_
EVT_07
Functional Multiplexing DSP DMA Register C (FUNC_MUX_DSP_DMA_C)
152
DSP Subsystem
Value
Description
These read-only bits return 0s when read.
0−27
Configuration bits for DMA event 12. Writing a value n to this
register maps peripheral request source n+1 to DSP DMA event
12. The value n must be between 0 and 27.
0−27
Configuration bits for DMA event 11. Writing a value n to this
register maps peripheral request source n+1 to DSP DMA event
11. The value n must be between 0 and 27.
0−27
Configuration bits for DMA event 10. Writing a value n to this
register maps peripheral request source n+1 to DSP DMA event
10. The value n must be between 0 and 27.
0−27
Configuration bits for DMA event 9. Writing a value n to this
register maps peripheral request source n+1 to DSP DMA event
9. The value n must be between 0 and 27.
0−27
Configuration bits for DMA event 8. Writing a value n to this
register maps peripheral request source n+1 to DSP DMA event
8. The value n must be between 0 and 27.
0−27
Configuration bits for DMA event 7. Writing a value n to this
register maps peripheral request source n+1 to DSP DMA event
7. The value n must be between 0 and 27.
This global control register (see Figure 78 and Table 56) is a 32-bit read/write
register. Use this OMAP configuration register to set the peripheral request
associated with DMA events 13 through 18.
SPRU890A