Texas Instruments OMAP5910 Reference Manual
  1. Manuals
  2. Brands
  3. Texas Instruments Manuals
  4. Controller
  5. OMAP5910
  6. Reference manual
Texas Instruments OMAP5910 Reference Manual

Texas Instruments OMAP5910 Reference Manual

Dual-core processor memory interface traffic controller
Hide thumbs Also See for OMAP5910:
Table of Contents

Advertisement

Quick Links

Download this manual See also: Reference Manual
OMAP5910 Dual-Core Processor
Memory Interface Traffic Controller
Reference Guide
Literature Number: SPRU673
October 2003

Advertisement

Table of Contents
loading

Related Manuals for Texas Instruments OMAP5910

Summary of Contents for Texas Instruments OMAP5910

  • Page 1 OMAP5910 Dual-Core Processor Memory Interface Traffic Controller Reference Guide Literature Number: SPRU673 October 2003...
  • Page 2 TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products...
  • Page 3 40 hexadecimal (decimal 64): 40h. Related Documentation From Texas Instruments The following documents describe the OMAP5910 device and related peripherals. Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com.
  • Page 4 Trademarks Related Documentation From Texas Instruments / Trademarks OMAP5910 Dual-Core Processor Universal Serial Bus (USB) and Frame Adjustment Counter (FAC) Reference Guide (literature number SPRU677) OMAP5910 Dual-Core Processor Clock Generation and System Reset Management Reference Guide (literature number SPRU678) OMAP5910 Dual-Core Processor General-Purpose Input/Output (GPIO)

  • Page 5: Table Of Contents

    ........Interfacing Memories With the OMAP5910 Device .
  • Page 6 Figures Figures TC Block Diagram ............. . Traffic Controller .
  • Page 7 Tables Tables Controller Access Mode and Data Access Width ........Device Types Associated With Chip-Select .
  • Page 8 SPRU673...

  • Page 9: Introduction

    OMAP5910 system memory resources (SRAM, SDRAM, flash, ROM, etc.). The TC also manages accesses by the MPU or the USB host. The USB host is an internal OMAP5910 peripheral connected on the local bus, so the TC contributes to managing USB host accesses.

  • Page 10: Tc Block Diagram

    Introduction Figure 1. TC Block Diagram DSP private OMAP5910 DSP private peripherals peripheral Timers (3) DSP public peripherals Watchdog timer McBSP1 Level1/2 interrupt handlers TMS320C55x DSP McBSP3 (instruction cache, SARAM, DARAM, DMA, DSP public (shared) peripheral bus MCSI1 H/W accelerators)

  • Page 11: Traffic Controller

    Introduction Figure 2. Traffic Controller To/from To/from DSP MMU MPUI port MPUI Traffic controller ROM SRAM Flash MPU bus SBFlash Slow MPU TI Slow Slow I/F DMA MPUI- peripheral port bus (public) port Fast I/F DMA SDRAM Fast Fast port TIPB port MPU bus...

  • Page 12: Controller Access Mode And Data Access Width

    Single and burst access The memories accessed by the TC are separated into two groups: External memory is memory that is not part of the OMAP5910 device. It can be SDRAM, flash, ROM, RAM, etc. External memory is accessed using the external memory interface (EMIF). The TC has two separate memory interfaces to access the external memories.

  • Page 13: Memory Map

    Memory Map The TC provides each of the four hosts with: 8-/16-/32-bit single access and burst access, except the LCD controller channel. 16- or 32-bit access must start from the 16- or 32-bit boundary address. Size adaptation for 8-, 16-, or 32-bit words, with the requirement that address must be aligned on the correct bit boundary.

  • Page 14: Mpu Memory Map

    The interface to these memory devices is activated via internal address decoding. There is no external chip select. The OMAP5910 peripherals are mapped on the MPU memory space in two different segments: through STROBE0 (public peripherals) and STROBE1 (private peripherals). Each peripheral has a range of 2K bytes.
  • Page 15 Memory Map Table 3. MPU Memory Map (Continued) † Device Name Start Address End Address Size in Bytes Data Access DSP Processor Address Space DSP MPUI Interface MPUI Port RAM E000:0000 E0FF:FFFF 16M bytes 16/32 R/W MPUI DSP Peripherals I/O Space E100:0000 E101:FFFF 128K bytes...
  • Page 16 Memory Map Table 3. MPU Memory Map (Continued) † Device Name Start Address End Address Size in Bytes Data Access MPU Address Space (Continued) Reserved E102:0004 EFFF:FFFF Reserved F000:0000 FFFD:0000 MPU Public TIPB Peripherals (Strobe 0) UART1 FFFB:0000 FFFB:07FF 2K bytes 8 R/W UART2 FFFB:0800...
  • Page 17 MPU Private TIPB Peripherals (Strobe 1) MPU level 2 interrupt handler FFFE:0000 FFFE:07FF 2K bytes 32 R/W ULPD power management FFFE:0800 FFFE:0FFF 2K bytes 16 R/W OMAP5910 configuration FFFE:1000 FFFE:17FF 2K bytes 32 R/W Die ID FFFE:1800 FFFE:1FFF 2K bytes 32 R/W Reserved...

  • Page 18: Memory Interfaces

    Memory Interfaces Table 3. MPU Memory Map (Continued) † Device Name Start Address End Address Size in Bytes Data Access MPU Private TIPB Peripherals (Strobe 1) (Continued) MPU Timer 3 FFFE:C700 FFFE:C7FF 256 bytes 32 R/W MPU watchdog timer FFFE:C800 FFFE:C8FF 256 bytes 32 R/W...

  • Page 19: Internal Memory Interface

    IMIF Priority Handler This memory interface has two software-selectable priority algorithms for resolving simultaneous access requests: least recently used and dynamic priority. The priority scheme is shared with the EMIFS and EMIFF and is set OMAP5910 configuration registers (bit LRU_SEL FUNC_MUX_CTRL_0).

  • Page 20: Imif Operation

    15 −0 Flash data bus from external device † FLASH.CS2 and FLASH.BAA are multiplexed on the same device pin. Pin function is selected using the OMAP5910 configu- ration register, FUNC_MUX_CRTL_0. The FLASH.CS2 functionality is default. Memory Interface Traffic Controller SPRU673...

  • Page 21: Emifs Priority Handler

    3 −0 External byte enable † FLASH.CS2 and FLASH.BAA are multiplexed on the same device pin. Pin function is selected using the OMAP5910 configu- ration register, FUNC_MUX_CRTL_0. The FLASH.CS2 functionality is default. Note: OMAP5910 multiplexes the FLASH.CS2 and FLASH.BAA pin functionality to the same device pin.

  • Page 22: Emifs Operation

    Memory Interfaces The low-priority queue order is: Local bus DMA (all channels excluding LCD) The high-priority queue order is: Local bus DMA transfer involving channels other than LCD channel Fixed priority is a special case of dynamic priority. To create a fixed priority, all time-out registers must have a value of 0.

  • Page 23: Device Initialization

    Memory Interfaces 3.2.3 Device Initialization Depending on the flash memory or RAM device associated with each chip- select, the EMIFS interface must be initialized. If the device used is a flash, the flash may have to be initialized in the correct protocol to achieve maximum performance.

  • Page 24: Asynchronous Read Operation

    In synchronous modes a selectable retiming feature enables read data to be latched by a delayed EMIFS reference clock. The retiming feature accounts for delays through the OMAP5910 input/output pins by feeding back FLASH.CLK to offer optimum data and clock alignment. You can select the retiming mode using the RT bit in the EMIFS chip-select configuration registers.

  • Page 25: Asynchronous Page Mode Read Operation

    Memory Interfaces Figure 3. Asynchronous 16-Bit Read Operation on a 16-Bit Width Device TC Clock (internal) EMIFS Ref (internal) FLASH.CLK N cycles FLASH.CS_[X] FLASH.ADV FLASH.A(24:1) Address valid FLASH.D(15:0) Valid data D0 FLASH.OE FLASH.BE(1:0) High FLASH.RDY 3.2.6 Asynchronous Page Mode Read Operation The asynchronous page mode read operation is similar to the asynchronous read, except that the number of wait states is different between the first access and the subsequent accesses within the page.

  • Page 26: Asynchronous Page Mode 8X16-Bit Read Operation On A 16-Bit Width Device

    Memory Interfaces As in asynchronous mode, device interface signals are referenced to the internal EMIFS reference clock, which is divided from the TC clock using FCLKDIV in the EMIF slow interface configuration register. The FLASH.CLK signal is not externally driven in asynchronous page operating mode. Figure 4 shows typical timing for an asynchronous page mode 8x16-bit read operation on a 16-bit width device with RDWST = 2, PGWST = 0, FCLKDIV = 01, and RDMODE = 2.

  • Page 27: Burst Read Operation

    The synchronous read mode is selected for each device by setting the RDMODE configuration bit field to 100b. In this mode of operation, FLASH.CLK is driven on the OMAP5910 device pin. Both AMD burst flash and Intel burst flash have three modes of operation:...
  • Page 28 Note: Intel Burst Flash Operation Intel burst flash (such as the Intel 28FxxxK3, 28FxxxK18, and 28FxxxW18), requires the OMAP5910 FLASH.RDY pin to be pulled up instead of being tied to the flash’s WAIT pin. The traffic controller properly handles all timing requirements without the WAIT pin assertion.

  • Page 29: Synchronous Burst Read With Page Alignment

    Memory Interfaces Figure 6. Synchronous Burst Read With Page Alignment Synchronous burst read operation (1/2) TC clock FLASH.CLK (FCLKDIV=1) 1 TC clock cycles (RDWST+1)xFCLKDIV TC clock cycles FLASH.CLK (FCLKDIV=2) 2 TC clock cycles (RDWST+1)xFCLKDIV TC clock cycles FLASH.CLK (FCLKDIV=4) 4 TC clock cycles (RDWST+1)xFCLKDIV TC clock cycles FLASH.CLK (FCLKDIV=6)

  • Page 30: Asynchronous Write With We Operation

    Memory Interfaces 3.2.8 Asynchronous Write With WE Operation The asynchronous write is used for both file flash and burst flash devices. Figure 7 shows the timing diagram. Burst write operation is not supported. Figure 7. Asynchronous Write With WE Operation FLASH.CLK (internal) Address valid...

  • Page 31: Emifs Dual-Port Ram Interface Mode

    3.2.9 EMIFS Dual-Port RAM Interface Mode The OMAP5910 EMIFS includes a programmable mode associated with the FLASH.CS2 chip select pin to support external devices that require a valid flash address before chip select is active. An example of such a device is a dual port RAM (DPRAM).

  • Page 32: Emiff Priority Handler

    EMIFF Priority Handler This memory interface has two software-selectable priority algorithms for resolving simultaneous access requests: least recently used and dynamic priority. The priority scheme is shared with the EMIFS and IMIF and it is set in OMAP5910 configuration registers (bit LRU_SEL FUNC_MUX_CTRL_0).

  • Page 33: Emiff Operation

    Memory Interfaces The low-priority queue order is: Local bus DMA (all channels including LCD) The high-priority queue order is: DMA transfer involving LCD channel Local bus DMA transfer involving channels other than LCD channel Fixed priority is a special case of dynamic priority. To create a fixed priority, all time-out registers must have a value of 0.

  • Page 34: Sdram Mode And Extended Mode Register Initialization

    MRS command on the pins of the SDRAM interface. When the command is issued, the content of the OMAP5910 MRS register is placed on the SDRAM address bus and latched by the SDRAM into its internal MRS register.

  • Page 35: Sdram Autorefresh Initialization

    SDRAM. The OMAP5910 device can support subdividing the autorefresh of the SDRAM into bursts of 1, 4, or 8 rows. It is recommended to set this parameter to 8 rows.

  • Page 36: Sdram Clock Disable

    Memory Interfaces beyond 64 milliseconds, and the SDRAM controller does not autorefresh during reset, data is corrupted. Setting the RFRSH_RST bit in the EMIF fast interface SDRAM configuration register 2 (EMIFF_SDRAM_CONFIG_2) avoids SDRAM data corruption for this case by automatically placing the SDRAM in self-refresh mode prior to warm reset being applied to the traffic controller.

  • Page 37: Sdram Write Single 32-Bit Word With Burst Stop

    Memory Interfaces Figure 8. SDRAM Write Single 32-Bit Word With Burst Stop ACTV0 WRITE STOP ACCESS_REG ACCESS_GRANT COMMAND ADDRESS B0/R0 B0/C0 Ignored C0+1 C0+2 CURRENT_COL C0+1 CURRENT_SIZE DVALID SAVE_ADD LAST_DATE WRITE (burst reduced to 2) is interrupted by a STOP command because no new request is pending. Note: SPRU673 Memory Interface Traffic Controller...

  • Page 38: Sdram Write Single 16-Bit Half-Word With Burst Stop

    Memory Interfaces Figure 9. SDRAM Write Single 16-Bit Half-Word With Burst Stop ACTV0 WRITE STOP ACCESS_REG ACCESS_GRANT COMMAND ADDRESS B0/R0 B0/C0 Ignored C0+1 CURRENT_COL CURRENT_SIZE DVALID SAVE_ADD LAST_DATE WRITE (burst reduced to 1) is interrupted by a STOP command because no new request is pending. Note: Memory Interface Traffic Controller SPRU673...

  • Page 39: Sdram Write Single 16-Bit Half-Word Followed By Write Burst

    Memory Interfaces Figure 10. SDRAM Write Single 16-Bit Half-Word Followed by Write Burst 8 ACTV0 WRITE WRITE STOP ACCESS_REG ACCESS_GRANT COMMAND ADDRESS B0/R0 B0/C0 B1/C1 C0+1 C1+1 C1+2 C1+3 C1+4 C1+5 C1+6 C1+7 C1+8 CURRENT_COL C1+1 C1+2 C1+3 C1+4 C1+5 C1+6 C1+7 Output column counter CURRENT_SIZE DVALID...

  • Page 40: Sdram Read Single 16-Bit Half-Word With Burst Stop

    Memory Interfaces Figure 11. SDRAM Read Single 16-Bit Half-Word With Burst Stop ACTV0 READ STOP ACCESS_REG ACCESS_GRANT COMMAND ADDRESS B0/R0 B0/C0 L = 3 C0+1 CURRENT_COL CURRENT_SIZE DVALID SAVE_ADD LAST_DATE READ (burst reduced to 1) is interrupted by a STOP command because no new request is pending. Note: Memory Interface Traffic Controller SPRU673...

  • Page 41: Sdram Read Single 16-Bit Half-Word Followed By Read Burst 8 Half-Word

    Memory Interfaces Figure 12. SDRAM Read Single 16-Bit Half-Word Followed by Read Burst 8 Half-Word ACTV0 READ READ STOP ACCESS_REG ACCESS_GRANT COMMAND ADDRESS B0/R0 B0/C0 B1/C1 L = 3 C0+1 C1+1 C1+2 C1+3 C1+4 C1+5 C1+6 C1+7 C1+8 CURRENT_COL C1+1 C1+2 C1+3 C1+4 C1+5 C1+6 C1+7 Output column counter CURRENT_SIZE...

  • Page 42: Sdram Write Burst 32-Bit Word Followed By Read Burst 8 Half-Word

    Memory Interfaces Figure 13. SDRAM Write Burst 32-Bit Word Followed by Read Burst 8 Half-Word ACTV0 WRITE READ STOP ACCESS_REG ACCESS_GRANT COMMAND ADDRESS B0/R0 B0/C0 B1/C1 L = 3 Ignored C0+1 C1+2 C1+1 C1+2 C1+3 C1+4 C1+5 C1+6 C1+7 C1+8 CURRENT_COL C0+1 C1+1 C1+2 C1+3 C1+4 C1+5 C1+6...

  • Page 43: Sdram Single Half-Word Followed By A Read Burst 6 Half-Words

    Memory Interfaces Figure 14. SDRAM Single Half-Word Followed by a Read Burst 6 Half-Words ACTV0 WRITE STOP ACTV0 WRIT STOP ACCESS_REG ACCESS_GRANT COMMAND ADDRESS B0/R0 B0/C0 B0/R0 B0/R5 C0+1 C5+1 C5+2 C5+3 C5+4 C5+5 C5+6 CURRENT_COL C5+1 C5+2 C5+3 C5+4 C5+5 CURRENT_SIZE DVALID...

  • Page 44: Sdram Read Burst 4 Half-Words Followed By A Write Burst 3 Half-Words

    Memory Interfaces Figure 15. SDRAM Read Burst 4 Half-Words Followed by a Write Burst 3 Half-Words STOP ACTV0 READ WRITE STOP ACCESS_REG ACCESS_GRANT COMMAND ADDRESS B0/R0 B0/C0 B1/C1 L = 3 C0+1 C0+2 C0+3 C0+4 C1+1 C1+2 C1+3 CURRENT_COL C0+1 C0+2 C0+3 C1+5 C1+6...

  • Page 45: Sdram Read Single Half-Word Followed By A Write Byte

    Memory Interfaces Figure 16. SDRAM Read Single Half-Word Followed by a Write Byte ACTV0 READ ACTV0 WRIT STOP ACCESS_REG ACCESS_GRANT COMMAND ADDRESS B0/R0 B0/C0 B0/R0 B0/R5 B0/C5 L = 3 DQMU DQMx DQML C0+1 C5+1 CURRENT_COL CURRENT_SIZE DVALID SAVE_ADD LAST_DATE READ (burst reduced to 1) is followed by a single-byte WRITE in the same bank but on a different page.

  • Page 46: Sdram Write Single Followed By Write Burst 6 On The Same Bank And Different Page

    Memory Interfaces Figure 17. SDRAM Write Single Followed by Write Burst 6 on the Same Bank and Different Page ACTV0 WRIT STOP ACTV0 WRIT STOP ACCESS_REG ACCESS_GRANT COMMAND ADDRESS B0/R0 B0/C0 B0/R0 B0/R5 C0+1 C5+1 C5+2 C5+3 C5+4 C5+5 C5+6 CURRENT_COL C5+1 C5+2 C5+3 C5+4 C5+5...

  • Page 47: Sdram Read Single Half-Word Followed By A Read Burst 8 With

    Memory Interfaces Figure 18. SDRAM Read Single Half-Word Followed by a Read Burst 8 With Page Crossing SPRU673 Memory Interface Traffic Controller...

  • Page 48: Traffic Controller Memory Interface Registers

    Traffic Controller Memory Interface Registers Traffic Controller Memory Interface Registers The OMAP5910 traffic controller base address is 0xFFFE:CC00. Table 9 lists the traffic controller registers. Table 10 through Table 28 describe the register bits. The EMIF slow interface configuration register provides access to EMIFS boot, operation, and power-down options (see Table 13).

  • Page 49: Imif Priority Register (Imif_Prio)

    Traffic Controller Memory Interface Registers Table 9. Traffic Controller Registers (Continued) Name Description Size Address Reset Value ENDIANISM Endianism 32 bits 0xFFFE:CC34 0x0000 0000 Location not used 0xFFFE:CC38 EMIFF_SDRAM_CONFIG_2 EMIF fast interface SDRAM 32 bits 0xFFFE:CC3C 0x0000 0003 configuration register 2 EMIFS_CFG_DYN_WAIT EMIF slow wait-state 32 bits...

  • Page 50: Emif Slow Priority Register (Emifs_Prio)

    Traffic Controller Memory Interface Registers Table 11. EMIF Slow Priority Register (EMIFS_PRIO) Reset Value Field Description Access 31−16 Reserved Reserved. These pins must always be written as 0. All 0s 15−12 LB host: Number of consecutive transfers while other ports are 0000 waiting + 1.

  • Page 51: Emif Slow Interface Configuration Register (Emifs_Config_Reg)

    Traffic Controller Memory Interface Registers Table 13. EMIF Slow Interface Configuration Register (EMIFS_CONFIG_REG) Reset Value Field Value Description Access 31−5 Reserved Read is undefined. Writes must be zero. All 0 Ready signal. This bit is a copy of the FLASH.RDY input pin as sampled by TC clock.

  • Page 52: Emif Slow Chip-Select Configuration Registers

    31−22 Reserved Read is undefined. Writes must be zero. All 0 Specifies how EMIFS handles addressing when performing 32-bit writes to the OMAP5910 16-bit data bus. The address is incremented for the second 16-bit access (default). The address is not incremented for the second 16-bit access.

  • Page 53: Memory Type

    Traffic Controller Memory Interface Registers Table 14. EMIF Slow Chip-Select Configuration Registers (EMIFS_CS0_CONFIG...EMIFS_CS3_CONFIG) (Continued) Reset Value Field Value Description Access Reserved Read is undefined. Writes must be zero. Retiming control register: The data is not retimed. The data coming from the external bus is retimed with the CLK.

  • Page 54: Wait Cycles Insertion

    Traffic Controller Memory Interface Registers Table 16. Wait Cycles Insertion RDWST Number of Cycles Inserted There is no automatic hardware adjustment of the programmed latencies when the system clock frequency changes. The following restrictions apply when synchronous burst read Intel protocol is selected: Only full-page burst mode is supported Only sequential data access order is supported...
  • Page 55 Traffic Controller Memory Interface Registers Table 17. EMIF Fast Interface SDRAM Configuration Register 1 (EMIFF_SDRAM_CONFIG) (Continued) Reset Value Field Value Description Access SDRAM power-down enable. Controls power-down state of SDRAM interface: SDRAM interface is not powered down. SDRAM interface is powered down. PWD is one of the prerequisites to meet TC idle.

  • Page 56: Sdram Internal Organization

    SDRAM. Data from SDRAM is double buffered. Data is first clocked on return clock from SDRAM, then with the OMAP5910 internal SDRAM clock. SLRF When set, places the SDRAM in self-refresh mode. Mode is automatically exited upon the generation of any SDRAM access.
  • Page 57 Traffic Controller Memory Interface Registers Table 18. SDRAM Internal Organization (Continued) Memory Size Number Of (M Bits) Banks SDRAM_TYPE Size Of Data Bus † 1010 1011 † 1100 1101 † 1110 1111 † Unavailable bank number (not supported). Do not use this setting. Table 19.

  • Page 58: Sdram Timing Requirements (See Parameter Definitions Below)

    Traffic Controller Memory Interface Registers Table 20. SDRAM Timing Requirements (see parameter definitions below) Meeting this Timing With SDRAM.CLK = SDRAM Timing 60 MHz (16.7 ns Requirements (ns) Period) ac Parameters (trwl) − − † Write is never interrupted by precharge command directly. ‡...

  • Page 59: Emif Fast Interface Sdram Mrs Register—Default (Emiff_Mrs)

    Reserved (must be set to 111, only full page burst length is supported). When the CONF_MOD_EMRS_CTRL bit field (bit 13) of the OMAP5910 control register (MOD_CONF_CTRL_0) is Note: set, the device reconfigures bank settings to write out the EMIFF_MRS register as EMRS commands (see Table 22).

  • Page 60: Emif Fast Interface Sdram Mrs Register—Emrs Mode (Emiff_Mrs)

    Traffic Controller Memory Interface Registers Table 22. EMIF Fast Interface SDRAM MRS Register—EMRS Mode (EMIFF_MRS) Reset Value Field Value Description Access 31−5 Reserved Read is undefined. Writes must be zero. Note 1 4−3 TCSR SDRAM EMRS register temperature compensated self-refresh setting: Note 1 70 degrees Celsius maximum case temperature 45 degrees Celsius maximum case temperature...

  • Page 61: Time-Out 1 Register (Timeout1)

    Traffic Controller Memory Interface Registers Table 23. Time-Out 1 Register (TIMEOUT1) Reset Value Field Description Access 31−24 Reserved Read is undefined. Writes must be zero. All 0 23−16 Local bus 0x00 15:8 Reserved Read is undefined. Writes must be zero. All 0 0x00 Table 24.
  • Page 62 Traffic Controller Memory Interface Registers Table 27. EMIF Fast Interface SDRAM Configuration Register 2 (EMIFF_SDRAM_CONFIG_2) Reset Value Field Value Description Access 31−2 Reserved Read is undefined. Writes must be zero. All 0 RFRSH_ SDRAM self-refresh on warm reset. RFRSH_RST determines what action the TC SDRAM controller takes toward setting SDRAM to self-refresh mode in the event of a warm system reset.

  • Page 63: Interfacing Memories With The Omap5910 Device

    Interfacing Memories With the OMAP5910 Device This section provides two examples of how to connect memories to the OMAP5910 device. Many scenarios can be considered using different kinds of memories. For flash memories, Intel and Hitachi products are used. For SDRAM and SRAM, Hitachi and Toshiba products are used, respectively.

  • Page 64: External Memory Interconnection Using Intel Flash Memory

    Interfacing Memories With the OMAP5910 Device Figure 19. External Memory Interconnection Using Intel Flash Memory OMAP5910 SDRAM GND fixed HM52Y64165F SDRAM_CLK (Hitachi) SDRAM.CKE 2.5 V−2.8 V SDRAM.RAS SDRAM.CAS SDRAM.WE SDRAM.DQMU DQMU SDRAM.DQML DQML SDRAM.D[15:0] DQ[15:0] SDRAM.BA[1:0] BA[1:0] SDRAM.A[11:0] A[11:0] SDRAM.A[12]...

  • Page 65: External Memory Interconnection Using Hitachi Flash Memory

    Interfacing Memories With the OMAP5910 Device Figure 20. External Memory Interconnection Using Hitachi Flash Memory OMAP5910 SDRAM GND Fixed HM52Y64165F SDRAM_CLK (Hitachi) SDRAM.CKE 2.5 V−2.8 V SDRAM.RAS SDRAM.CAS SDRAM.WE SDRAM.DQMU DQMU DQML SDRAM.DQML SDRAM.D[15:0] DQ[15:0] SDRAM.BA[1:0] BA[1:0] A[11:0] SDRAM.A[11:0] SDRAM.A[12]...
  • Page 66 Memory Interface Traffic Controller SPRU673...
  • Page 67 Index Index access, mode, traffic controller 14 EMIFF address, spaces, TI925T 16 autorefresh, initialization 37 asynchronous endianism conversion 38 read operation initialization 36 description 26 memory interfaces, traffic controller 33 page mode 27 operation 35 write, with WE operation 32 priority handler 34 SDRAM clock disable 38...
  • Page 68 Index traffic controller 15 timing control, EMIFS 25 features, traffic controller, connected hosts 15 flash memory Hitachi 67 OMAP1510, memory interfaces 65 Intel 65 operation asynchronous page mode read 27 asynchronous read 26 asynchronous write with WE 32 EMIFF 35 Hitachi flash memory 67 EMIFS 24 IMIF 22...
  • Page 69 Index TI925T 14 functions 11 internal memory, SRAM 14 TC, See traffic controller 14 memory interfaces 20 TI burst flash, operational modes 29 EMIFF 33 TI925T IMIF 21 address spaces 16 memory map 15 memory map 16 device types/chip−select 15 traffic controller, connected hosts 14 overview 11 traffic controller...
  • Page 70 SPRU673...
  • Page 71 TI Home Page and browse through to get the desired page. Products | Applications | Support | Site Map © Copyright 1995-2003 Texas Instruments Incorporated. All rights reserved. Trademarks | Privacy Policy | Terms of Use http://focus.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=spru678 [10/2/2003 2:16:07 PM]...
  • Page 72 Pricing/Availability • TI-RFid™ ASIC Packaging Microcontrollers Glossary Programmable Logic Training Military Webcasts Automotive Space Products FIFOs Products Applications Support Site Map © Copyright 1995-2003 Texas Instruments Incorporated. All rights reserved. Trademarks Privacy Policy Terms of Use http://www.ti.com/sc/docs/products/index.htm [10/2/2003 2:16:09 PM]...

Table of Contents