Texas Instruments OMAP5910 Reference Manual page 81

SPRU890A
The table walking logic starts an address translation by accessing a descriptor
from a first-level translation table (section 6.2.5). To determine the address of
the descriptor, add a first-level table index (taken from the virtual address) and
the base address of the first-level translation table (taken from the translation
table base registers TTB_MSB_REG and TTB_LSB_REG). The first-level
translation table divides the DSP memory space into 16 1MB-sections.
The contents of the first-level descriptor determine whether the section to
which the virtual address corresponds is further divided into pages or if the
section is directly linked to a physical memory section. In the latter case, the
descriptor provides a section base address which is joined to a section index
(taken from the virtual address) to generate a physical address.
When a section is further divided into pages, the first-level descriptor provides
a base address for a second-level translation table (section 6.2.6). A
descriptor is accessed from the second-level translation table to determine the
page base address corresponding to the virtual address. Determine the base
address of the descriptor by adding a second-level table index (taken from the
virtual address) and the second-level translation table base address. Finally,
the physical address is determined by adding a page base address provided
by the descriptor and a page index taken from the virtual address.
After an address translation has been carried out, the table walking logic
updates the selected TLB entry with the translation result. The victim pointer
selects this TLB entry, then selects the next unlocked entry to be replaced.
The table walking logic is enabled through the Control Register (CNTL_REG).
If the table walking logic is not enabled, an interrupt will be generated to the
MPU core on every TLB miss, see section 6.2.7 for more details.
Note:
When the table walking logic is enabled, the TLB cannot be manually
updated; you should not write to the LD_TLB_REG, TTB_H_REG,
TTB_L_REG, and LOCK_REG.
The DSP core can force the table walking logic to perform an address
translation pre-fetch before the occurrence of a TLB miss. For this, a pre-fetch
register is visible in DSP I/O memory space. The DSP initiates a pre-fetch by
writing the DSP virtual address tag to the pre-fetch register.
Note:
The table walking logic must be enabled to carry out the pre-fetch request.
DSP Memory Management Unit
DSP Subsystem 81