Texas Instruments OMAP5910 Reference Manual page 169

Table 63. DMA Channel Control Register (DMACCR) Field Descriptions (Continued)
Bits Field
6 PRIO
5 FS
4−0 SYNC
SPRU890A
Value Description
Channel priority bit. All six of the DMA channels are given a fixed
position and programmable priority level on the service chain of the
DMA controller. PRIO determines whether the associated channel
has a high priority or a low priority. High-priority channels are serviced
before low-priority channels.
0 Low priority.
1 High priority.
Frame/element synchronization bit. You can use the SYNC bits of
DMACCR to specify a synchronization event for the channel. The FS
bit determines whether the synchronization event initiates the transfer
of an element or an entire frame of data:
0 Element synchronization. When the selected synchronization event
occurs, one element is transferred in the channel. Each element
transfer waits for the synchronization event.
1 Frame synchronization. When the selected synchronization event
occurs, an entire frame is transferred in the channel. Each frame
transfer waits for the synchronization event.
(see Synchronization control bits. SYNC in DMACCR determines the
section peripheral request (for example, a serial port transmit request).
7.2.12.4)
A DSP subsystem reset selects SYNC = 00000b (no synchronization
event). When SYNC = 00000b, the DMA controller does not wait for
a synchronization event before beginning a DMA transfer in the
channel; channel activity begins as soon as the channel is enabled
(EN = 1).
If the DMA is configured to recognize a synchronization event (SYNC
is something other than 00000b) and the synchronization event
occurs before the channel is enabled, the synchronization event will
be latched and serviced as soon as the channel is enabled. If it is
preferable to ignore the synchronization events that occur before the
channel is enabled, then the SYNC field should be set to 00000b while
the channel is disabled.
Each peripheral request can be mapped to a specific DMA
synchronization event through the GDMA Handler. However, at reset,
a default mapping is implemented.
DSP DMA
DSP Subsystem 169