High-Level Data Memory Map For Dsp Subsystem; Dsp Dma Controller Architecture - Texas Instruments OMAP5910 Reference Manual

DSP DMA
7.2

DSP DMA Controller Architecture

7.2.1 Clock Control
7.2.2 Memory Map
Figure 65.

High-Level Data Memory Map for DSP Subsystem

Main data page 0
Main data page 1
Main data page 2
.
.
.
Main data page 127
124 DSP Subsystem
The DSP DMA controller is part of the DSP module within the DSP subsystem
(see section 1.2) and thus is clocked by the DSP subsystem clock, DSP_CK.
Section 12.2 describes the DSP subsystem clock.
Figure 65 is a high-level memory map for the DSP subsystem data memory
space. The diagram shows both the word addresses (23-bit addresses) used
by the DSP core and byte addresses (24-bit addresses) used by the DMA
controller.
Note:
Word addresses 00 0000h − 00 005Fh (which correspond to byte addresses
00 0000h − 00 00BFh) are reserved for the memory-mapped registers
(MMRs) of the DSP core.
Word addresses
(Hexadecimal ranges)
MMRs 00 0000-00 005F
00 0060-00 FFFF
01 0000-01 FFFF
02 0000-02 FFFF
.
.
.
7F 0000-7F FFFF
Figure 66 is an I/O space map for the DSP subsystem. The diagram shows
both the word addresses (16-bit addresses) used by the DSP core and byte
addresses (17-bit addresses) used by the DMA controller.
Byte addresses
Memory (Hexadecimal ranges)
00 0000-00 00BF
00 00C0-01 FFFF
02 0000-03 FFFF
04 0000-05 FFFF
FE 0000-FF FFFF
.
.
.
SPRU890A