Ps-Side: Ddr4 Sodimm Socket - Xilinx ZCU102 User Manual

I/O Voltage Rails
There are nine PL I/O banks available on the XCZU9EG MPSoC. The voltages applied to the
XCZU9EG MPSoC I/O banks used by the ZCU102 board are listed in
Table 3-2: I/O Voltage Rails
XCZU9EG
PL Bank 0
PL Bank 44
PL Bank 47
PL Bank 48
PL Bank 49
PL Bank 50
PL Bank 64
PL Bank 65
PL Bank 66
PL Bank 67
PS Bank 500
PS Bank 501
PS Bank 502
PS Bank 503
PS DDR Bank 504
Notes:
1. The ZCU102 board is shipped with V

PS-Side: DDR4 SODIMM Socket

[Figure 2-1, callout 2]
The PS-side memory is wired to the Zynq UltraScale+ DDRC hard memory controller. A
64-bit single rank DDR4 SODIMM with ECC (72-bit) is inserted into socket J1. The ZCU102
is shipped with a DDR4 SODIMM installed:
• Manufacturer: Kingston
• Part Number: KVR21SE15S8/4
• Description:
4GByte DDR4 SODIMM
°
Single Rank x8
°
512Mbit x 72-Bit
°
PC4-2133 260-Pin
°
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
Power Net Name Voltage
NA NA
V 3.3V
CC3V3
V 3.3V
CC3V3
V 3.3V
CC3V3
V 3.3V
CC3V3
V 3.3V
CC3V3
V 1.2V
CC1V2
(1)
V 1.8V
ADJ_FMC
(1)
V 1.8V
ADJ_FMC
(1)
V 1.8V
ADJ_FMC
V 1.8V
CCOPS
V 1.8V
CCOPS
V 1.8V
CCOPS
V 1.81V
CCOPS3
V 1.2V
CCO_PSDDR_504
set to 1.8V by the MSP430 system controller.
ADJ_FMC
www.xilinx.com
Chapter 3: Board Component Descriptions
Connected To
MPSoC Configuration Bank 0
GPIO DIP SW, PB SW, LEDs, 74.25 MHz CLK
GPIO PMOD0 (RT-ANG. FEMALE), PMOD1 (STR.
MALE), PL I2C1, TRACEDATA, 125 MHz CLK
TRACEDATA
HDMI Codec, SYSMON I2C, SFP CTRL, UART2, MSP430
UCA1
HDMI Codec, MSP430 GPIO, PL I2C0, PROTO. HDR. IO
DDR4 DQ[0:15], DDR4 ADDR/CTRL, USER_SI570 CLK
FMC_HPC1 LA BUS, HDMI TX
FMC_HPC0 LA BUS, HDMI REC CLK
FMC_HPC0 LA BUS, SFP REC CLK
QSPI LWR, QSPI UPR, UART1, MIO_I2C0, MIO_I2C1,
MIO_RXD/TXD, CAN IF
MIO_SD IF, MIO_PMU IF, MIO_DP IF
MIO_ENET, MIO_USB
PS CONFIGURATION IF
DDR4 SODIMM IF
Table 3-2.
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