Ps-Side: Ddr4 Sodimm Socket - Xilinx ZCU106 User Manual

I/O Voltage Rails
The XCZU7EV MPSoC PL I/O bank voltages on the ZCU106 board are listed in
Table 3-2: I/O Voltage Rails
XCZU7EV Power Net Name
PL Bank 28
PL Bank 64
PL Bank 65
PL Bank 66
PL Bank 67
PL Bank 68
PL Bank 87
PL Bank 88
PS Bank 500
PS Bank 501
PS Bank 502
PS Bank 503
PS Bank 504
Notes:
1. The ZCU106 board is shipped with V

PS-Side: DDR4 SODIMM Socket

[Figure 2-1, callout 2]
The PS-side memory is wired to the Zynq UltraScale+ DDRC bank 504 hard memory
controller. A 64-bit single rank DDR4 SODIMM with ECC (72-bit) is inserted into socket J1.
The ZCU106 is shipped with a DDR4 SODIMM installed:
• Manufacturer: Kingston
• Part Number: KVR21SE15S8/4
• Description:
4 GByte DDR4 SODIMM
°
Single rank x8
°
512 Mbit x 72-Bit
°
PC4-2133 260-Pin
°
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
Voltage
(1)
V 1.8V
ADJ_FMC
V 1.2V
CC1V2
V 1.2V
CC1V2
V 1.2V
CC1V2
(1)
V 1.8V
ADJ_FMC
(1)
V 1.8V
ADJ_FMC
V 3.3V
CC3V3
V 3.3V
CC3V3
V 1.8V
CCOPS
V 1.8V
CCOPS
V 1.8V
CCOPS
V 1.8V
CCOPS3
V 1.2V
CCO_PSDDR_504
set to 1.8V by the MSP430 system controller.
ADJ_FMC
www.xilinx.com
Chapter 3: Board Component Descriptions
Connected To
FMC_HPC1 LA BUS, PMOD0
DDR4 DQ[0:31]
DDR4 DQ[32:63]
DDR4 ADDR/CTRL, GPIO LED, GPIO SW, PMOD1
FMC_HPC0 LA BUS, GPIO DIP SW
FMC_HPC0 LA BUS, SFP REC CLOCK
HDMI, MSP430 GPIO
TRACE DEBUG CONNECTOR
CAN, UART0/1, I2C0/1, QSPI LWR/UPR
SDIO, PMU_GPO[0:5], DP
ENET, USB_DATA[0:7], USB_CTRL
PS CONFIG I/F
DDR4 72-BIT SODIMM I/F
Send Feedback
Figure 3-2.
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