I/O Voltage Rails; Mb Ddr3 Component Memory - Xilinx SP605 Hardware User's Manual

Chapter 1: SP605 Evaluation Board

I/O Voltage Rails

There are four available banks on the XC6SLX45T-3FGG484 device. Banks 0, 1, and 2 are
connected for 2.5V I/O. Bank 3 is used for the 1.5V DDR3 component memory interface of
Spartan-6 FPGA's hard memory controller. The voltage applied to the FPGA I/O banks
used by the SP605 board is summarized in
Table 1-2: I/O Voltage Rail of FPGA Banks
See the

2. 128 MB DDR3 Component Memory

The SP605 128 MB 16-bit wide DDR3 memory consists of a single 1 Gb x 16 SDRAM U42
wired to Bank 3 (V
memory controller is used for data transfer across the DDR3 memory interface's 16-bit
data path using SSTL15 signaling.
•
•
•
The SP605 board supports the "standard" VCCINT setting of 1.20V ± 5%. This setting
provides memory controller block (MCB) performance of 667 MT/s for DDR3 memory.
The SP605 XC6SLX45T FPGA DDR interface performance is documented in the Spartan-6
FPGA Data Sheet: DC and Switching Characteristics (DS162).
Signal integrity is maintained through DDR3 resistor terminations and memory on-die
terminations (ODT), as shown in
Table 1-3: Termination Resistor Requirements
16
FPGA Bank
0
1
2
3
Xilinx Spartan-6 FPGA documentation
= 1.5V) of the U1 XC6SLX45T FPGA. The Spartan-6 FPGA hard
cco
Manufacturer: Micron
Part Number: MT41J64M16LA-187E
Description:
• 1 Gb: 128 MB (64 Mb x 16)
• 1.5V 96-ball FBGA
• Performance: up to DDR3-1066
Signal Name
MEM1_A[14:0]
MEM1_BA[2:0]
MEM1_RAS_N
MEM1_CAS_N
MEM1_WE_N
MEM1_CS_N
MEM1_CKE
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Table 1-2.
I/O Voltage Rail
2.5V
2.5V
2.5V
1.5V
for more information.
Table 1-3 and Table 1-4.
Board Termination
49.9Ω to V
49.9Ω to V
49.9Ω to V
49.9Ω to V
49.9Ω to V
100Ω to GND
4.7 KΩ to GND
[Ref 1]
On-Die Termination
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TT
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TT
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TT
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TT
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TT
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SP605 Hardware User Guide
UG526 (v1.9) February 14, 2019