Ddr4 Component Memory - Xilinx KCU105 User Manual

Table 1-3: I/O Bank Voltage Rails
FPGA (U1) Bank
Bank 0
HP Bank 44
HP Bank 45
HP Bank 46
HP Bank 47
HP Bank 48
HR Bank 64
HR Bank 65
HP Bank 66
HP Bank 67
HP Bank 68

DDR4 Component Memory

[Figure 1-2, callout 2]
The 2 GB DDR4 component memory system is comprised of four 256 Mb x 16 DDR4 SDRAM
devices (Micron EDY4016AABG-DR-F-D) located at U60-U63. This memory system is
connected to the XCKU040 HP banks 44, 45, and 46. The DDR4 0.6V VTT termination voltage
(net DDR4_VTT) is sourced from the TI TPS51200DR linear regulator U24. The connections
between the DDR4 component memories and the XCKU040 banks 44, 45, and 46 are listed
in Table 1-4.
Table 1-4: DDR4 Memory Connections to the FPGA
FPGA Schematic Net
(U1) Pin
AE23 DDR4_DQ0
AG20 DDR4_DQ1
AF22 DDR4_DQ2
AF20 DDR4_DQ3
AE22 DDR4_DQ4
AD20 DDR4_DQ5
AG22 DDR4_DQ6
AE20 DDR4_DQ7
AJ24 DDR4_DQ8
AG24 DDR4_DQ9
AJ23 DDR4_DQ10
KCU105 Board User Guide
UG917 (v1.4) September 25, 2015
Power Supply Rail
Net Name
VCC1V8_FPGA
VCC1V2_FPGA
VCC1V2_FPGA
VCC1V2_FPGA
VADJ_1V8_FPGA
VADJ_1V8_FPGA
VCC1V8_FPGA
VCC1V8_FPGA
VADJ_1V8_FPGA
VADJ_1V8_FPGA
VADJ_1V8_FPGA
I/O Standard
Name
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
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Chapter 1: KCU105 Evaluation Board Features
Voltage
1.8V
1.2V
1.2V
1.2V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
Component Memory
Pin #
G2
F7
H3
H7
H2
H8
J3
J7
A3
B8
C3
Pin Name Ref. Des.
DQL0 U60
DQL1 U60
DQL2 U60
DQL3 U60
DQL4 U60
DQL5 U60
DQL6 U60
DQL7 U60
DQU0 U60
DQU1 U60
DQU2 U60
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