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INTEL ITANIUM ARCHITECTURE Manual

INTEL ITANIUM ARCHITECTURE Manual (604 pages)

Brand: INTEL | Category: Software | Size: 2 MB

Table of Contents

Table of Contents
4
1 About this Manual

8
2 Base IA-32 Instruction Reference

18
- Additional Intel ® Itanium ® Faults
  18
- Register Encodings Associated with the +Rb, +Rw, and +Rd Nomenclature
  20
  - Operation
    22
  - Flags Affected
    25
  - FPU Flags Affected
    25
- Bit Offset for BIT[EAX,21]
  25
- Memory Bit Indexing
  25
- Exception Mnemonics, Names, and Vector Numbers
  26
  - Floating-Point Exceptions
    27
  - Base Instruction Reference
    27
- Floating-Point Exception Mnemonics and Names
  27
- Information Returned by CPUID Instruction
  85
- Version Information in Registers EAX
  86
- Feature Flags Returned in EDX Register
  87
- FPATAN Zeros and Nans
  156
- FPREM Zeros and Nans
  158
- FPREM1 Zeros and Nans
  161
- FSUB Zeros and Nans
  190
- FSUBR Zeros and Nans
  193
- FYL2X Zeros and Nans
  206
- FYL2XP1 Zeros and Nans
  208
- IDIV Operands
  211
- INT Cases
  225
- LAR Descriptor Validity
  260
- LEA Address and Operand Sizes
  265
- Repeat Conditions
  345
  - Intel ® MMX™ Technology Instruction Reference
    406
- Operation of the MOVD Instruction
  408
- Operation of the MOVQ Instruction
  410
- Operation of the PACKSSDW Instruction
  412
- Operation of the PACKUSWB Instruction
  415
- Operation of the PADDW Instruction
  417
- Operation of the PADDSW Instruction
  420
- Operation of the PADDUSB Instruction
  423
- Operation of the PAND Instruction
  426
- Operation of the PANDN Instruction
  428
- Operation of the PCMPEQW Instruction
  430
- Operation of the PCMPGTW Instruction
  433
- Operation of the PMADDWD Instruction
  436
- Operation of the PMULHW Instruction
  438
- Operation of the PMULLW Instruction
  440
- Operation of the por Instruction
  442
- Operation of the PSLLW Instruction
  444
- Operation of the PSRAW Instruction
  447
- Operation of the PSRLW Instruction
  450
- Operation of the PSUBW Instruction
  453
- Operation of the PSUBSW Instruction
  456
- Operation of the PSUBUSB Instruction
  459
- High-Order Unpacking and Interleaving of Bytes with the PUNPCKHBW Instruction
  462
- Low-Order Unpacking and Interleaving of Bytes with the PUNPCKLBW Instruction
  465
- Operation of the PXOR Instruction
  468
3 IA-32 Intelmmx™ Technology Instruction Reference

470
- About the Intel ® SSE Architecture
  470
- IA-32 SSE Instructions
  470
4 IA-32 SSE Instruction Reference

470
- Single Instruction Multiple Data
  471
- New Data Types
  471
- Packed Single-FP Data Type
  471
  - Extended Instruction Set
    472
- SSE Register Set
  472
- Scalar Operation
  472
  - Instruction Group Review
    473
- Packed Operation
  473
- Packed Shuffle Operation
  475
- Unpack High Operation
  476
- Unpack Low Operation
  476
  - IEEE Compliance
    481
    
    Real Number System
    481
- Binary Real Number System
  482
- Binary Floating-Point Format
  483
- Real Number Notation
  483
- Real Numbers and Nans
  485
- Denormalization Process
  485
  - Operating on Nans
    487
  - Data Formats
    488
    
    Memory Data Formats
    488
    
    SSE Register Data Formats
    488
- Four Packed FP Data in Memory (at Address 1000H)
  488
- Results of Operations with NAN Operands
  488
- Precision and Range of SSE Datatype
  489
- Real Number and Nan Encodings
  489
  - Instruction Formats
    490
  - Instruction Prefixes
    490
- SSE Instruction Behavior with Prefixes
  490
- SIMD Integer Instructions - Behavior with Prefixes
  490
- Cacheability Control Instruction Behavior with Prefixes
  490
  - Reserved Behavior and Software Compatibility
    491
  - Notations
    491
- Key to SSE Naming Convention
  492
  - SIMD Integer Instruction Set Extensions
    569
  - Cacheability Control Instructions
    582
Index

590

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