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Signal Description
Table 6-5.
Reset and Miscellaneous Signals (Sheet 2 of 2)
Signal Name
RESET_OBS#
RSTIN#
RSVD
RSVD_NCTF
RSVD_TP
SM_DRAMRST#
6.4
PCI Express* Based Interface Signals
Table 6-6.
PCI Express* Based Interface Signals
Signal Name
PEG_ICOMPI
PEG_ICOMPO
PEG_RBIAS
PEG_RCOMPO
PEG_RX[15:0]
PEG_RX#[15:0]
PEG_TX[15:0]
PEG_TX#[15:0]
6.5
DMI—Processor to PCH Serial Interface
Table 6-7.
DMI—Processor to PCH Serial Interface
Signal Name
DMI_RX[3:0]
DMI_RX#[3:0]
DMI_TX[3:0]
DMI_TX#[3:0]
Datasheet, Volume 1
Description
This signal is an indication of the processor being reset.
Reset In: When asserted, this signal will asynchronously
reset the processor logic. This signal is connected to the
PLTRST# output of the PCH.
RESERVED. Must be left unconnected on the board.
Intel does not recommend a test point on the board for
this land.
RESERVED/Non-Critical to Function: Pin for package
mechanical reliability. A test point may be placed on the
board for this land.
RESERVED-Test Point. A test point may be placed on the
board for this land.
DDR3 DRAM Reset: Reset signal from processor to
DRAM devices. One common to all channels.
Description
PCI Express Current Compensation.
PCI Express Current Compensation.
PCI Express Resistor Bias Control.
PCI Express Resistance Compensation.
PCI Express Receive Differential Pair.
PCI Express Transmit Differential Pair.
Description
DMI input from PCH: Direct Media Interface receive
differential pair.
DMI output to PCH: Direct Media Interface transmit
differential pair.
Direction
Type
Asynch
O
CMOS
I
CMOS
O
DDR3
Direction
Type
I
Analog
I
Analog
I
Analog
I
Analog
PCI
I
Express
PCI
O
Express
Direction
Type
I
DMI
O
DMI
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