Intel Xeon E3-1125C User Manual
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Intel Xeon E3-1125C User Manual

Intel Xeon E3-1125C User Manual

With intel communications chipset 8910 development kit
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®
Intel
Xeon
with Intel
8910 Development Kit
User Guide
October 2012
®
Processor E3-1125C
®
Communications Chipset
Order No.: 328009-001US

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Summary of Contents for Intel Xeon E3-1125C

  • Page 1 ® ® Intel Xeon Processor E3-1125C ® with Intel Communications Chipset 8910 Development Kit User Guide October 2012 Order No.: 328009-001US...
  • Page 2 PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND...

  • Page 3: Table Of Contents

    2.3.5 Connect Power..................31 2.4 Turning On and Resetting the Board................31 3.0 Overview of BIOS Features..................32 3.1 Introduction......................32 3.1.1 PCI Auto-Configuration................32 ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No.: 328009-001US...
  • Page 4 CRB 2 DIMM/CH DDR3 Topology................11 DIMM Population Within a Channel for Two Slots per Channel........12 ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit PCIe Headers..................16 SMBus Block Diagram....................20 Memory Sockets......................22 SPI In-Circuit Programming..................23 Dediprog: SPI Flash Offset..................30 Offset Setting......................30...
  • Page 5 ® ® Intel Xeon Processor E3-1125C PCIe Lane Reversal..........15 ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit PCIe Configuration................16 ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit Default Header Configuration............16 Rear Panel I/O Connectors..................16...

  • Page 6: Introduction

    The Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 ® ® ® Development Kit (CRB) hardware design is based on the Intel Xeon and Intel ® Core™ Processor For Communications Infrastructure connected to the Intel ® ® Communications Chipset 89xx Series. The CRB design supports one Intel Xeon ®...

  • Page 7: Warnings And Cautions

    Kit Contents Feature Description ® ® ® CRB board PCB assembled with a BGA device down for the Intel Xeon and Intel Core™ Processor For Communications Infrastructure and device down for ® Intel Communications Chipset 89xx Series with a passive heatsink.

  • Page 8: Features Summary

    Crystal Forest—Introduction Feature Description GbE PHY plug-in cards • Intel® Ethernet Server Adapter X520-T2, Dual-port 10G Bast T NIC • Intel® Ethernet Server Adapter X520-SR2, Dual-port SFP+ SR Optics Stand Acrylic stand for board plus pads Additional peripherals 8 x Standoffs and 16 x screws...

  • Page 9: Related Documents

    Introduction—Crystal Forest Feature Description ® ® ® Clocking CK420 for delivery of differential clocks to Intel Xeon and Intel Core™ ® Processor For Communications Infrastructure and Intel Communications Chipset 89xx Series DB1900 clock buffer for additional 100-MHz differential clocks BIOS Two 16-pin SOIC SPI Socket for Flash support.

  • Page 10: Processors And Chipset

    IA-PC HPET (High Precision Event Timers) Contact your Intel representative for the latest Specification, Revision 0.98a version of this item. Intel® ICH Family Real Time Clock (RTC) Accuracy Intel appnote AP-728 and Considerations Under Test Front Panel I/O Connectivity Design Guide http://www.formfactors.org/DeveloperResources.asp...

  • Page 11: Supported Memory

    For two slot per channel configurations, the CRB requires DIMMs within a channel to be populated starting with the DIMMs farthest from the processor in a “fill-farthest” approach. ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No.: 328009-001US...

  • Page 12: Thermal And Mechanical Components

    The CRB provides fan headers for the processors that includes 12V. Heatsink The CRB supports heatsink mounting requirements. continued... ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 Order No.: 328009-001US...

  • Page 13: Real Time Clock (Rtc), Cmos Sram, And Battery

    The active heatsink is powered by the platform. For details on the processor and PCH heatsink, see the Thermal/Mechanical Design Guidelines. The ® passive heatsink for the Intel Communications Chipset 89xx Series requires no power. Physical and Mechanical Board Specifications The CRB is approximately 12 inches long by 12 inches wide.

  • Page 14: On-Board I/O Connectors

    Location J5B1 PCI Express* Slot Processor The PCI Express ports comply with PCI Express* Base Specification, Rev. 2.0a. continued... ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 Order No.: 328009-001US...

  • Page 15: Pch Endpoint Pcie Configuration

    PCI Express Hot-Plug is not supported. 1.12 PCH EndPoint PCIe Configuration ® This section provides details on how to configure the PCIe for the supported Intel Communications Chipset 89xx Series SKU. ® Table 7. Intel Communications Chipset 89xx Series SKUs ®...

  • Page 16: Rear Panel I/O Connectors

    Crystal Forest—Introduction ® ® ® Table 10. Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit PCIe Configuration Header Description J6E2 J6E2 must be Open for the PCH with BIOS V35 or later. J3F2 Jumper must be Closed (inserted).

  • Page 17: On-Board Power Connectors

    — Requires a complete OS boot when the system wakes 1.17 Wake Events • Power switch • Wake on LAN (WoL) from GbE (PCH EndPoint/connector) or PCIe port ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No.: 328009-001US...

  • Page 18: Fan Power Connections

    The ability to enable and disable APIC and ACPI is present in the BIOS. Control is Control also required for OS plug-and-play features. The BIOS supports the following ACPI states: continued... ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 Order No.: 328009-001US...

  • Page 19: Acpi

    SMBus The following figure provides a summary of the SMBus structure and address information supplemental to the CRB schematics. ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No.: 328009-001US...

  • Page 20: Ddr3 Vref Control Circuit

    KΩ / 12.1 KΩ 1% resistor voltage dividers. This must be considered if calculating the resulting VREF voltage for particular settings of the potentiometer. ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 Order No.: 328009-001US...

  • Page 21: Crb Setup

    An additional source for CRB configuration and setup options is via board-level stuffing resistors. These settings may be visible via the CRB schematics. These stuffing resistor settings should not be altered unless directed to do so by Intel; changes require a board rework.

  • Page 22: Memory Module Plug-In

    ® • Slot 2 is a x8 link with a x16 connector (option for x16 link muxed with the Intel Communications Chipset 89xx Series End-Point). Some systems may have issues training with Slot 2. If you encounter issues with Slot 2, try a different slot.

  • Page 23: Rear Panel Connectors

    CRB Setup—Crystal Forest • Intel recommends that you install the Matrox* video card in slot 3, and you connect the bottom DVI port to the monitor's VGA connection with a DVI-to-VGA adapter. 2.3.3 Rear Panel Connectors • Connect a USB or PS/2 keyboard and/or mouse to the rear panel connectors.
  • Page 24 This is what it looks like with door 1 opened: (Note: SPI flash should be preinstalled) 2. Follow the same steps to open door 2. ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 Order No.: 328009-001US...
  • Page 25 4. Align SOIC with guide slots. It is not necessary to apply pressure. 5. Align the pin 1 indicator on the IC with the pin 1 dot on the board silkscreen. ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No.: 328009-001US...
  • Page 26 Crystal Forest—CRB Setup 6. Gently close door 2, and then door 1. ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 Order No.: 328009-001US...

  • Page 27: Spi Flash Memory Removal

    2. Use tweezers to gently remove the device from the socket. 3. Gently close the socket doors to avoid damage. ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No.: 328009-001US...

  • Page 28: Dediprog: Spi Flash Memory Programming

    Even though the SPI flash can be programmed with or without power on the board, it is best to do it with the board powered down. ® 1. Disconnect the Intel Communications Chipset 89xx Series SPI interface to SPI flash by removing the shunt from SPI_PROG jumper (J2J1) to program either SPI0 or SPI1.
  • Page 29 Rom01_4M.bin Note: See the File Descriptions section of the BIOS release notes to verify BIOS version and file names. ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No.: 328009-001US...

  • Page 30: Dediprog: Spi Flash Offset

    Verify to verify the SPI. Make sure the checksum matches. Figure 10. Offset Verification 11. Done: Disconnect the Dediprog cable before booting the system. ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 Order No.: 328009-001US...

  • Page 31: Gbe Eeprom Devices

    “POWER,” and the other button is the reset button, labeled “RESET.” Note: The power button is also used to wake a system that is in a sleep state. ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No.: 328009-001US...

  • Page 32: Overview Of Bios Features

    Introduction The BIOS is stored in the SPI device on the PCH SPI bus. If SPI flash programming is necessary, contact your Intel technical representative about the SPI programming details. The BIOS displays a message during POST identifying the type of BIOS and a revision code.

  • Page 33: Language Support

    USB device should be selected as the priority device in the Boot Priority menu. Have the USB device plugged in when changing this BIOS setting. ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No.: 328009-001US...

  • Page 34: Changing The Boot Device

    If only the supervisor password is set, pressing the <Enter> key at the password prompt of the BIOS Setup program allows the user restricted access to Setup. ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 Order No.: 328009-001US...

  • Page 35: Boot Flow

    Once the BIOS destination is determined, the PCH will determine the location of BIOS on the SPI device through the base address that is defined in the SPI flash descriptor. ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No.: 328009-001US...

  • Page 36: Appendix A Technical Reference

    Appendix A Technical Reference Detailed memory information for addressable memory and memory maps are in the ® ® ® Intel Communications Chipset 89xx Series Datasheet and in the Intel Xeon ® Intel Core™ Processors For Communications Infrastructure Datasheet. Caution: Do not move jumpers when the power is on. Always turn off the power and unplug the power cord before changing a jumper setting.

  • Page 37: Processor Straps - Jumper Settings

    Open: Sets the DMI termination voltage to Voltage Vcc/2 Open (GPIO17) Closed: Sets the DMI termination voltage to continued... ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No.: 328009-001US...

  • Page 38: Miscellaneous Jumper Settings

    89xx Series (Serial Port #2) <-> Serial Port SIO Enable J3A2 Black Shunt [1-2] Open: Disable SIO (LPC_FRAME_SIO_N) Closed: Enable SIO continued... ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 Order No.: 328009-001US...

  • Page 39: Reserved Headers

    Shunt 2-3: VTT_SA VID0 pin pulled high (IVB) DMI Voltage J8K4 Black Shunt [2-3] Shunt 1-2: 1.0V (Ivy Bridge processor) CPU_SNB_IVB_N ® Shunt 2-3: 1.05V (2nd Generation Intel Core™ Mobile Processor) Table 20. Reserved Headers Ref Des Colour Default Setting J1F8 Blue...

  • Page 40: Smbus Headers

    SMBus PCH - DIMM Header J7E3 Open Header on DIMM SMBus SMBus PCH - Clock Header J5A2 Open Header on Clock SMBus ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 Order No.: 328009-001US...

  • Page 41: Voltage Measurement Headers

    5 V Main Standby DS4K2 Green VCC5_PS_STBY voltage present Voltage 5 V Aux Power DS9B1 Green VCC5_AUX voltage present continued... ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No.: 328009-001US...
  • Page 42 The CPU Thermal Trip output signal is active PCH Wake DS2F1 Green PCH Wake Signal is active WDT Time-out DS2E5 Yellow PCH WDT_TOUT is active ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 Order No.: 328009-001US...

  • Page 43: Power Supply Connectors

    ATX power on indicator LED hard drive LED Hard drive LED driver FP_HD_LED_N FP_LED_YLW_N User defined LED driver output output (GP27) continued... ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No.: 328009-001US...

  • Page 44: Memory Resources

    A.11 Memory Resources Detailed memory information for addressable memory and memory maps are in the ® ® ® Intel Communications Chipset 89xx Series Datasheet and in the Intel Xeon ® Intel Core™ Processors For Communications Infrastructure External Design Specification A.12 Interrupts Interrupts can be routed through the I/O xAPIC, which supports 24 interrupts.

  • Page 45: Pch Gpio Mapping

    GPIO9 Native General Purpose I/O Port 9. Not Multiplexed continued... ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No.: 328009-001US...
  • Page 46 1. Used by LPC devices, such as Super I/ O chips, to request DMA or bus master access. This signal is typically connected continued... ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 Order No.: 328009-001US...

  • Page 47: Intel Communications Chipset 8910 Development Kit Pcie Headers..................................................................................16

    ADR (Asynchronous DRAM Refresh) trigger on platform. Only supported if processor supports ADR. HARDWARE activation mechanism that continued... ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No.: 328009-001US...
  • Page 48 Note: 1. OC# pins are 3.3V and NOT 5V tolerant 2. OC# pins must be shared between ports continued... ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 Order No.: 328009-001US...
  • Page 49 If BBS1 interface is not used, the signals can be used as GPIO Port 51. GPIO52 Native CORE General Purpose I/O Port 52. Not Multiplexed. continued... ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No.: 328009-001US...
  • Page 50 OC# pins are 3.3V and NOT 5 V tolerant. OC# pins must be shared between ports OC#[3:0] can only be used for EHCI controller #1 continued... ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 Order No.: 328009-001US...
  • Page 51 2. When the multiplexed GPIO is used as GPIO functionality, care should be taken to ensure the signal is stable in its inactive state of the native functionality, immediately after reset until it is initialized to GPIO functionality. Multiplexed signals is visible or Intel reserved. ®...
  • Page 52 4. The functionality that is multiplexed with the GPIO may not be used in desktop configuration. 5. In a ME disabled system, GPIO31 may be used as ACPRESENT from the EC. ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 Order No.: 328009-001US...

  • Page 53: Appendix B Error Messages And Led Codes

    Memory Detection PEIM (Memory Init) 0x21 Memory Installed 0x31 CPU PEIM (CPU Init) 0x32 CPU PEIM (Cache Init) 0x33 continued... ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No.: 328009-001US...
  • Page 54 DXE USB detect 0x9C DXE USB enable 0x9D DXE IDE begin 0xA1 DXE IDE reset 0xA2 DXE IDE detect 0xA3 continued... ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 Order No.: 328009-001US...

  • Page 55: Port 0X80 Error Codes

    Port 0x80 Error Codes Description Port 0x80 Code Memory Type Invalid 0x50 Memory Speed Invalid 0x50 Memory SPD failure 0x51 continued... ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No.: 328009-001US...
  • Page 56 S3 OS Wake Vector error 0xEB Recovery PPI not found 0xF8 Recovery capsule not found 0xF9 Invalid Recovery Capsule 0xFA ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 Order No.: 328009-001US...

  • Page 57: Port 0X80 Error Debug

    Memory size has decreased since the last boot. If no memory was removed then memory may be bad. No Boot Device Available System did not find a device to boot. ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No.: 328009-001US...

  • Page 58: Appendix C Board Reference Diagrams

    Crystal Forest—Board Reference Diagrams Appendix C Board Reference Diagrams Figure 11. Top View ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 Order No.: 328009-001US...

  • Page 59: Ddr3 Memory Components

    Board Reference Diagrams—Crystal Forest Figure 12. DDR3 Memory Components ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No.: 328009-001US...

  • Page 60: Pcie Slots

    Crystal Forest—Board Reference Diagrams Figure 13. PCIe Slots Figure 14. PECI & Thermal Diode Components ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 Order No.: 328009-001US...

  • Page 61: Leds And Power Button Switches

    Board Reference Diagrams—Crystal Forest Figure 15. LEDs and Power Button Switches ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No.: 328009-001US...

  • Page 62: Power Supply Headers

    Crystal Forest—Board Reference Diagrams Figure 16. Power Supply Headers ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 Order No.: 328009-001US...

  • Page 63: Smbus Headers

    Board Reference Diagrams—Crystal Forest Figure 17. SMBus Headers ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No.: 328009-001US...

  • Page 64: Configuration Jumper Locations (1 Of 2)

    Crystal Forest—Board Reference Diagrams Figure 18. Configuration Jumper Locations (1 of 2) ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 Order No.: 328009-001US...
  • Page 65 Board Reference Diagrams—Crystal Forest Figure 19. Configuration Jumper Locations (2 of 2) ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No.: 328009-001US...

  • Page 66: Intel ® Communications Chipset 89Xx Series Straps

    Crystal Forest—Board Reference Diagrams ® Figure 20. Intel Communications Chipset 89xx Series Straps ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 Order No.: 328009-001US...

  • Page 67: Front Panel

    ® ® ® Figure 21. Intel Xeon and Intel Core™ Processor For Communications Infrastructure Straps Figure 22. Front Panel ® ® ® Intel Xeon Processor E3-1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No.: 328009-001US...

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