Specific Masks And Factor Flags For Interrupt; Interrupt Vectors - Epson E0C6001 Technical Manual

E0C6001 TECHNICAL HARDWARE
Specific masks and
factor flags for inter-
rupt
Table 4.9.2
Interrupt mask registers and
interrupt factor flags

Interrupt vectors

I-54
The interrupt factor flags can be masked by the correspond-
ing interrupt mask registers. The interrupt mask registers
are read/write registers. They are enabled (interrupt en-
abled) when 1 is written to them, and masked (interrupt
disabled) when 0 is written to them. After an initial reset,
the interrupt mask register is set to 0.
Table 4.9.2 shows the correspondence between interrupt
mask registers and interrupt factor flags.
Interrupt Mask Register
EIT2
EIT8
EIT32
EIK03*
EIK02*
EIK01*
EIK00*
* There is an interrupt mask register for each input port pin.
When an interrupt request is input to the CPU, the CPU
begins interrupt processing. After the program being exe-
cuted is suspended, interrupt processing is executed in the
following order:
The address data (value of the program counter) of the
program step to be executed next is saved on the stack
(RAM).
The interrupt request causes the value of the interrupt
vector (page 1, 01H–07H) to be loaded into the program
counter.
The program at the specified address is executed (execu-
tion of interrupt processing routine).
Note
The processing in steps 1 and 2, above, takes 12 cycles of the
CPU system clock.
(0EBH D2) IT2
(0EBH D1) IT8
(0EBH D0) IT32
(0E8H D3)
(0E8H D2)
IK0
(0E8H D1)
(0E8H D0)
Interrupt Factor Flag
(0EFH D2)
(0EFH D1)
(0EFH D0)
(0EDH D0)