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ADC YH,i
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
ADC YL,i
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
S1C6200/6200A CORE CPU MANUAL
Add with carry immediate data i to YH
ADC YH,i
YH
YH + i
to i
+ C
3
0
1 0 1 0 0 0 1 0 i
MSB
IV
7
C –
Set if a carry is generated; otherwise, reset.
Z –
Set if the result is zero; otherwise, reset.
D –
Not affected
I –
Not affected
Adds the carry bit and immediate data i to YH, the four high-order bits of YHL.
ADC YH,3
YH register
1010
C flag
1
Z flag
0
Add with carry immediate data i to YL
ADC YL,i
YL
YL + i
to i
+ C
3
0
1 0 1 0 0 0 1 1 i
MSB
IV
7
C –
Set if a carry is generated; otherwise, reset.
Z –
Set if the result is zero; otherwise, reset.
D –
Not affected
I –
Not affected
Adds the carry bit and immediate data i to YL, the four low-order bits of YHL.
ADC YL,3
YL register
1010
C flag
1
Z flag
0
i
i
i
A20H to A2FH
3
2
1
0
LSB
ADC YH,6
1110
0100
0
0
i
i
i
A30H to A3FH
3
2
1
0
LSB
ADC YL,2
1110
0000
0
0
EPSON
3 INSTRUCTION SET
1
0
1
1
31
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