Epson 6200A Core Cpu Manual page 19

Core cpu cmos 4-bit single chip microcomputer
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S1C6200
Clock
Status
Instruction
5-clock Instrruction
S1C6200A
Clock
Status
Instruction
5-clock Instrruction
Status:
S1C6200/6200A
System clock
CPU clock
Status
Instruction
5-clock Instrruction
Status:
S1C6200/6200A CORE CPU MANUAL
12-clock Instrruction
Interrupt
Interrupt processing:
12-clock Instrruction
Interrupt
Interrupt processing:
Fetch
Execute
Note:
Fig. 2.5.3.1 Interrupt timing during execution
HALT
Fetch
Execute
Note:
Fig. 2.5.3.2 Interrupt timing in the HALT mode
INT1 (*1)
12-clock instruction
... 13 to 25 clock cycles
7-clock instruction
... 13 to 20 clock cycles
5-clock instruction
... 13 to 18 clock cycles
INT1 (*1)
12-clock instruction
... 12.5 to 24.5 clock cycles
7-clock instruction
... 12.5 to 19.5 clock cycles
5-clock instruction
... 12.5 to 17.5 clock cycles
INT1 and INT2 are dummy instructions
(*1)
(*2)
Branches to the top of the interrupt service routine
INT1 (*1)
Interrupt
Interrupt processing: 14 to 15 clock cycles
(*1)
INT1 and INT2 are dummy instructions
Branches to the top of the interrupt service routine
(*2)
EPSON
2 MEMORY AND OPERATIONS
INT2 (*1)
JP (*2)
INT2 (*1)
JP (*2)
INT2 (*1)
JP (*2)
13

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