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LD X,e
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
LD XH,r
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
S1C6200/6200A CORE CPU MANUAL
Load immediate data e into X-register
LD X,e
XH
e
to e
, XL
e
7
4
3
1 0 1 1 e
e
e
7
6
MSB
I
5
C –
Not affected
Z –
Not affected
D –
Not affected
I –
Not affected
Loads 8-bit immediate data e into register X.
XH register
0000
XL register
1011
Load r-register into XH
LD XH,r
XH
r
1 1 1 0 1 0 0 0 0 1 r
MSB
V
5
C –
Not affected
Z –
Not affected
D –
Not affected
I –
Not affected
Loads the contents of the r-register into the four high-order bits of register X.
LD XH,A
XH register
0000
A register
1011
Memory (MY)
0110
to e
0
e
e
e
e
e
5
4
3
2
1
0
LSB
LD X,6FH
0110
1111
r
1
0
LSB
LD XH,MY
1011
1011
0110
EPSON
3 INSTRUCTION SET
B00H to BFFH
E84H to E87H
0110
1011
0110
57
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