Epson 6200A Core Cpu Manual page 28

3 INSTRUCTION SET
Mne-
Page Operand
monic
B A
67 PSET p 1 1
68 PUSH F 1 1
68 r 1 1
69 XH 1 1
69 XL 1 1
70 XP 1 1
70 YH 1 1
71 YL 1 1
71 YP 1 1
72 RCF 1 1
72 RDF 1 1
73 RET 1 1
73 RETD e 0 0
74 RETS 1 1
74 RLC r 1 0
75 RRC r 1 1
75 RST F, i 1 1
76 RZF 1 1
76 SBC r, i 1 1
77 r, q 1 0
77 SCF 1 1
78 SCPX MX, r 1 1
78 SCPY MY, r 1 1
79 SDF 1 1
79 SET F, i 1 1
80 SLP 1 1
80 SUB r, q 1 0
81 SZF 1 1
81 XOR r, i 1 1
82 r, q 1 0
22
Operation Code
9 8 7 6 5 4 3 2 1 0
1 0 0 1 0 p4 p3 p2 p1 p0
1 1 1 1 0 0 1 0 1 0
1 1 1 1 0 0 0 0 r1 r0
1 1 1 1 0 0 0 1 0 1
1 1 1 1 0 0 0 1 1 0
1 1 1 1 0 0 0 1 0 0
1 1 1 1 0 0 1 0 0 0
1 1 1 1 0 0 1 0 0 1
1 1 1 1 0 0 0 1 1 1
1 1 0 1 0 1 1 1 1 0
1 1 0 1 0 1 1 0 1 1
1 1 1 1 0 1 1 1 1 1
0 1 e7 e6 e5 e4 e3 e2 e1 e0
1 1 1 1 0 1 1 1 1 0
1 0 1 1 1 1 r1 r0 r1 r0
1 0 1 0 0 0 1 1 r1 r0
1 1 0 1 0 1 i3 i2 i1 i0
1 1 0 1 0 1 1 1 0 1
0 1 0 1 r1 r0 i3 i2 i1 i0
1 0 1 0 1 1 r1 r0 q1 q0
1 1 0 1 0 0 0 0 0 1
1 1 0 0 1 1 1 0 r1 r0
1 1 0 0 1 1 1 1 r1 r0
1 1 0 1 0 0 0 1 0 0
1 1 0 1 0 0 i3 i2 i1 i0
1 1 1 1 1 1 1 0 0 1
1 0 1 0 1 0 r1 r0 q1 q0
1 1 0 1 0 0 0 0 1 0
0 1 0 0 r1 r0 i3 i2 i1 i0
1 0 1 1 1 0 r1 r0 q1 q0
Flag
Clock
I D Z C
5 NBP p4, NPP
5 SP SP-1, M(SP)
5 SP SP-1, M(SP)
5 SP SP-1, M(SP)
5 SP SP-1, M(SP)
5 SP SP-1, M(SP)
5 SP SP-1, M(SP)
5 SP SP-1, M(SP)
5 SP SP-1, M(SP)
7 C 0
7 D 0 (Decimal Adjuster OFF)
7 PCSL M(SP), PCSH
SP SP+3
12 PCSL M(SP), PCSH
SP SP+3, M(X)
12 PCSL M(SP), PCSH
SP SP+3, PC
7 d3 d2, d2
5 d3 C, d2
7 F F i3~i0
7 Z 0
7 r r-i3~i0-C
7 r r-q-C
7 C 1
7 M(X) M(X)-r-C, X
7 M(Y) M(Y)-r-C, Y
7 D 1 (Decimal Adjuster ON)
7 F FVi3~i0
5 SLEEP (stop oscillation)
7 r r-q
7 Z 1
7 r r i3~i0
7 r r q
EPSON
Operation
p3~p0
F
r
XH
XL
XP
YH
YL
YP
M(SP+1), PCP M(SP+2)
M(SP+1), PCP M(SP+2)
e3~e0, M(X+1) e7~e4, X
M(SP+1), PCP M(SP+2)
PC+1
d1, d1 d0, d0 C, C d3
d3, d1 d2, d0 d1, C d0
X+1
Y+1
S1C6200/6200A CORE CPU MANUAL
X+2