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LD r,YL
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
LD r,YP
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
S1C6200/6200A CORE CPU MANUAL
Load YL into r-register
LD r,YL
r
YL
1 1 1 0 1 0 1 1 1 0 r
MSB
V
5
C –
Not affected
Z –
Not affected
D –
Not affected
I –
Not affected
Loads the four low-order bits of register Y into the r-register.
LD B,YL
YL register
0000
B register
0110
Memory (MX)
1011
Load YP into r-register
LD r,YP
r
YP
1 1 1 0 1 0 1 1 0 0 r
MSB
V
5
C –
Not affected
Z –
Not affected
D –
Not affected
I –
Not affected
Loads the 4-bit page part of index register IY into the r-register.
LD MY,YP
YP register
1010
B register
1100
Memory (MY)
0110
r
EB8H to EBBH
1
0
LSB
LD MX,YL
0000
0000
0000
0000
1011
0000
r
EB0H to EB3H
1
0
LSB
LD B,YP
1010
1010
1100
1010
1010
1010
EPSON
3 INSTRUCTION SET
55
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