Epson 6200A Core Cpu Manual page 58

3 INSTRUCTION SET
LD r,SPH
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
LD r,SPL
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
52
Load SPH into r-register
LD r,SPH
r SPH
1 1 1 1 1 1 1 0 0 1 r
MSB
V
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Loads the four high-order bits of the stack pointer into the r-register.
LD MX,SPH
SPH 0111
A register 0000
Memory (MX) 1100
Load SPL into r-register
LD r,SPL
r SPL
1 1 1 1 1 1 1 1 0 1 r
MSB
V
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Loads the four low-order bits of the stack pointer into the r-register.
LD A,SPL
SPL 1001
A register 0010
Memory (MY) 0000
r FE4H to FE7H
1 0
LSB
LD A,SPH
0111 0111
0000 0111
0111 0111
r FF4H to FF7H
1 0
LSB
LD MY,SPL
1001 1001
1001 1001
0000 1001
EPSON
S1C6200/6200A CORE CPU MANUAL